
graph:     file format elf64-littleaarch64


Disassembly of section .init:

00000000004005f0 <_init>:
  4005f0:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4005f4:	910003fd 	mov	x29, sp
  4005f8:	94000048 	bl	400718 <call_weak_fn>
  4005fc:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400600:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400610 <.plt>:
  400610:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400614:	f0000090 	adrp	x16, 413000 <__FRAME_END__+0xf84c>
  400618:	f947fe11 	ldr	x17, [x16, #4088]
  40061c:	913fe210 	add	x16, x16, #0xff8
  400620:	d61f0220 	br	x17
  400624:	d503201f 	nop
  400628:	d503201f 	nop
  40062c:	d503201f 	nop

0000000000400630 <memcpy@plt>:
  400630:	900000b0 	adrp	x16, 414000 <memcpy@GLIBC_2.17>
  400634:	f9400211 	ldr	x17, [x16]
  400638:	91000210 	add	x16, x16, #0x0
  40063c:	d61f0220 	br	x17

0000000000400640 <malloc@plt>:
  400640:	900000b0 	adrp	x16, 414000 <memcpy@GLIBC_2.17>
  400644:	f9400611 	ldr	x17, [x16, #8]
  400648:	91002210 	add	x16, x16, #0x8
  40064c:	d61f0220 	br	x17

0000000000400650 <__libc_start_main@plt>:
  400650:	900000b0 	adrp	x16, 414000 <memcpy@GLIBC_2.17>
  400654:	f9400a11 	ldr	x17, [x16, #16]
  400658:	91004210 	add	x16, x16, #0x10
  40065c:	d61f0220 	br	x17

0000000000400660 <__gmon_start__@plt>:
  400660:	900000b0 	adrp	x16, 414000 <memcpy@GLIBC_2.17>
  400664:	f9400e11 	ldr	x17, [x16, #24]
  400668:	91006210 	add	x16, x16, #0x18
  40066c:	d61f0220 	br	x17

0000000000400670 <abort@plt>:
  400670:	900000b0 	adrp	x16, 414000 <memcpy@GLIBC_2.17>
  400674:	f9401211 	ldr	x17, [x16, #32]
  400678:	91008210 	add	x16, x16, #0x20
  40067c:	d61f0220 	br	x17

0000000000400680 <puts@plt>:
  400680:	900000b0 	adrp	x16, 414000 <memcpy@GLIBC_2.17>
  400684:	f9401611 	ldr	x17, [x16, #40]
  400688:	9100a210 	add	x16, x16, #0x28
  40068c:	d61f0220 	br	x17

0000000000400690 <free@plt>:
  400690:	900000b0 	adrp	x16, 414000 <memcpy@GLIBC_2.17>
  400694:	f9401a11 	ldr	x17, [x16, #48]
  400698:	9100c210 	add	x16, x16, #0x30
  40069c:	d61f0220 	br	x17

00000000004006a0 <__isoc99_scanf@plt>:
  4006a0:	900000b0 	adrp	x16, 414000 <memcpy@GLIBC_2.17>
  4006a4:	f9401e11 	ldr	x17, [x16, #56]
  4006a8:	9100e210 	add	x16, x16, #0x38
  4006ac:	d61f0220 	br	x17

00000000004006b0 <printf@plt>:
  4006b0:	900000b0 	adrp	x16, 414000 <memcpy@GLIBC_2.17>
  4006b4:	f9402211 	ldr	x17, [x16, #64]
  4006b8:	91010210 	add	x16, x16, #0x40
  4006bc:	d61f0220 	br	x17

00000000004006c0 <putchar@plt>:
  4006c0:	900000b0 	adrp	x16, 414000 <memcpy@GLIBC_2.17>
  4006c4:	f9402611 	ldr	x17, [x16, #72]
  4006c8:	91012210 	add	x16, x16, #0x48
  4006cc:	d61f0220 	br	x17

Disassembly of section .text:

00000000004006d0 <_start>:
  4006d0:	d280001d 	mov	x29, #0x0                   	// #0
  4006d4:	d280001e 	mov	x30, #0x0                   	// #0
  4006d8:	aa0003e5 	mov	x5, x0
  4006dc:	f94003e1 	ldr	x1, [sp]
  4006e0:	910023e2 	add	x2, sp, #0x8
  4006e4:	910003e6 	mov	x6, sp
  4006e8:	580000c0 	ldr	x0, 400700 <_start+0x30>
  4006ec:	580000e3 	ldr	x3, 400708 <_start+0x38>
  4006f0:	58000104 	ldr	x4, 400710 <_start+0x40>
  4006f4:	97ffffd7 	bl	400650 <__libc_start_main@plt>
  4006f8:	97ffffde 	bl	400670 <abort@plt>
  4006fc:	00000000 	.inst	0x00000000 ; undefined
  400700:	00402870 	.word	0x00402870
  400704:	00000000 	.word	0x00000000
  400708:	004031b8 	.word	0x004031b8
  40070c:	00000000 	.word	0x00000000
  400710:	00403238 	.word	0x00403238
  400714:	00000000 	.word	0x00000000

0000000000400718 <call_weak_fn>:
  400718:	f0000080 	adrp	x0, 413000 <__FRAME_END__+0xf84c>
  40071c:	f947f000 	ldr	x0, [x0, #4064]
  400720:	b4000040 	cbz	x0, 400728 <call_weak_fn+0x10>
  400724:	17ffffcf 	b	400660 <__gmon_start__@plt>
  400728:	d65f03c0 	ret
  40072c:	00000000 	.inst	0x00000000 ; undefined

0000000000400730 <deregister_tm_clones>:
  400730:	900000a0 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  400734:	9101a000 	add	x0, x0, #0x68
  400738:	900000a1 	adrp	x1, 414000 <memcpy@GLIBC_2.17>
  40073c:	9101a021 	add	x1, x1, #0x68
  400740:	eb00003f 	cmp	x1, x0
  400744:	540000a0 	b.eq	400758 <deregister_tm_clones+0x28>  // b.none
  400748:	f0000001 	adrp	x1, 403000 <main+0x790>
  40074c:	f9412c21 	ldr	x1, [x1, #600]
  400750:	b4000041 	cbz	x1, 400758 <deregister_tm_clones+0x28>
  400754:	d61f0020 	br	x1
  400758:	d65f03c0 	ret
  40075c:	d503201f 	nop

0000000000400760 <register_tm_clones>:
  400760:	900000a0 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  400764:	9101a000 	add	x0, x0, #0x68
  400768:	900000a1 	adrp	x1, 414000 <memcpy@GLIBC_2.17>
  40076c:	9101a021 	add	x1, x1, #0x68
  400770:	cb000021 	sub	x1, x1, x0
  400774:	9343fc21 	asr	x1, x1, #3
  400778:	8b41fc21 	add	x1, x1, x1, lsr #63
  40077c:	9341fc21 	asr	x1, x1, #1
  400780:	b40000a1 	cbz	x1, 400794 <register_tm_clones+0x34>
  400784:	f0000002 	adrp	x2, 403000 <main+0x790>
  400788:	f9413042 	ldr	x2, [x2, #608]
  40078c:	b4000042 	cbz	x2, 400794 <register_tm_clones+0x34>
  400790:	d61f0040 	br	x2
  400794:	d65f03c0 	ret

0000000000400798 <__do_global_dtors_aux>:
  400798:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  40079c:	910003fd 	mov	x29, sp
  4007a0:	f9000bf3 	str	x19, [sp, #16]
  4007a4:	900000b3 	adrp	x19, 414000 <memcpy@GLIBC_2.17>
  4007a8:	3941a260 	ldrb	w0, [x19, #104]
  4007ac:	35000080 	cbnz	w0, 4007bc <__do_global_dtors_aux+0x24>
  4007b0:	97ffffe0 	bl	400730 <deregister_tm_clones>
  4007b4:	52800020 	mov	w0, #0x1                   	// #1
  4007b8:	3901a260 	strb	w0, [x19, #104]
  4007bc:	f9400bf3 	ldr	x19, [sp, #16]
  4007c0:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4007c4:	d65f03c0 	ret

00000000004007c8 <frame_dummy>:
  4007c8:	17ffffe6 	b	400760 <register_tm_clones>

00000000004007cc <print_adjmatrix>:
  4007cc:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4007d0:	910003fd 	mov	x29, sp
  4007d4:	a90153f3 	stp	x19, x20, [sp, #16]
  4007d8:	aa0803f4 	mov	x20, x8
  4007dc:	aa0003f3 	mov	x19, x0
  4007e0:	f0000000 	adrp	x0, 403000 <main+0x790>
  4007e4:	9109a000 	add	x0, x0, #0x268
  4007e8:	97ffffb2 	bl	4006b0 <printf@plt>
  4007ec:	b9002fbf 	str	wzr, [x29, #44]
  4007f0:	1400000b 	b	40081c <print_adjmatrix+0x50>
  4007f4:	b9802fa0 	ldrsw	x0, [x29, #44]
  4007f8:	8b000260 	add	x0, x19, x0
  4007fc:	3941e000 	ldrb	w0, [x0, #120]
  400800:	2a0003e1 	mov	w1, w0
  400804:	f0000000 	adrp	x0, 403000 <main+0x790>
  400808:	9109c000 	add	x0, x0, #0x270
  40080c:	97ffffa9 	bl	4006b0 <printf@plt>
  400810:	b9402fa0 	ldr	w0, [x29, #44]
  400814:	11000400 	add	w0, w0, #0x1
  400818:	b9002fa0 	str	w0, [x29, #44]
  40081c:	b9408660 	ldr	w0, [x19, #132]
  400820:	b9402fa1 	ldr	w1, [x29, #44]
  400824:	6b00003f 	cmp	w1, w0
  400828:	54fffe6b 	b.lt	4007f4 <print_adjmatrix+0x28>  // b.tstop
  40082c:	52800140 	mov	w0, #0xa                   	// #10
  400830:	97ffffa4 	bl	4006c0 <putchar@plt>
  400834:	b9002fbf 	str	wzr, [x29, #44]
  400838:	14000022 	b	4008c0 <print_adjmatrix+0xf4>
  40083c:	b9802fa0 	ldrsw	x0, [x29, #44]
  400840:	8b000260 	add	x0, x19, x0
  400844:	3941e000 	ldrb	w0, [x0, #120]
  400848:	2a0003e1 	mov	w1, w0
  40084c:	f0000000 	adrp	x0, 403000 <main+0x790>
  400850:	9109e000 	add	x0, x0, #0x278
  400854:	97ffff97 	bl	4006b0 <printf@plt>
  400858:	b9002bbf 	str	wzr, [x29, #40]
  40085c:	14000010 	b	40089c <print_adjmatrix+0xd0>
  400860:	b9802ba2 	ldrsw	x2, [x29, #40]
  400864:	b9802fa1 	ldrsw	x1, [x29, #44]
  400868:	aa0103e0 	mov	x0, x1
  40086c:	d37ef400 	lsl	x0, x0, #2
  400870:	8b010000 	add	x0, x0, x1
  400874:	d37ff800 	lsl	x0, x0, #1
  400878:	8b020000 	add	x0, x0, x2
  40087c:	91009000 	add	x0, x0, #0x24
  400880:	b8607a61 	ldr	w1, [x19, x0, lsl #2]
  400884:	f0000000 	adrp	x0, 403000 <main+0x790>
  400888:	910a0000 	add	x0, x0, #0x280
  40088c:	97ffff89 	bl	4006b0 <printf@plt>
  400890:	b9402ba0 	ldr	w0, [x29, #40]
  400894:	11000400 	add	w0, w0, #0x1
  400898:	b9002ba0 	str	w0, [x29, #40]
  40089c:	b9408660 	ldr	w0, [x19, #132]
  4008a0:	b9402ba1 	ldr	w1, [x29, #40]
  4008a4:	6b00003f 	cmp	w1, w0
  4008a8:	54fffdcb 	b.lt	400860 <print_adjmatrix+0x94>  // b.tstop
  4008ac:	52800140 	mov	w0, #0xa                   	// #10
  4008b0:	97ffff84 	bl	4006c0 <putchar@plt>
  4008b4:	b9402fa0 	ldr	w0, [x29, #44]
  4008b8:	11000400 	add	w0, w0, #0x1
  4008bc:	b9002fa0 	str	w0, [x29, #44]
  4008c0:	b9408660 	ldr	w0, [x19, #132]
  4008c4:	b9402fa1 	ldr	w1, [x29, #44]
  4008c8:	6b00003f 	cmp	w1, w0
  4008cc:	54fffb8b 	b.lt	40083c <print_adjmatrix+0x70>  // b.tstop
  4008d0:	aa1403e3 	mov	x3, x20
  4008d4:	aa1303e1 	mov	x1, x19
  4008d8:	d2804400 	mov	x0, #0x220                 	// #544
  4008dc:	aa0003e2 	mov	x2, x0
  4008e0:	aa0303e0 	mov	x0, x3
  4008e4:	97ffff53 	bl	400630 <memcpy@plt>
  4008e8:	a94153f3 	ldp	x19, x20, [sp, #16]
  4008ec:	a8c37bfd 	ldp	x29, x30, [sp], #48
  4008f0:	d65f03c0 	ret

00000000004008f4 <create_1>:
  4008f4:	d111c3ff 	sub	sp, sp, #0x470
  4008f8:	a9007bfd 	stp	x29, x30, [sp]
  4008fc:	910003fd 	mov	x29, sp
  400900:	f9000bf3 	str	x19, [sp, #16]
  400904:	aa0003f3 	mov	x19, x0
  400908:	b90463bf 	str	wzr, [x29, #1120]
  40090c:	b9046fbf 	str	wzr, [x29, #1132]
  400910:	14000017 	b	40096c <create_1+0x78>
  400914:	b9046bbf 	str	wzr, [x29, #1128]
  400918:	1400000e 	b	400950 <create_1+0x5c>
  40091c:	b9846ba2 	ldrsw	x2, [x29, #1128]
  400920:	b9846fa1 	ldrsw	x1, [x29, #1132]
  400924:	aa0103e0 	mov	x0, x1
  400928:	d37ef400 	lsl	x0, x0, #2
  40092c:	8b010000 	add	x0, x0, x1
  400930:	d37ff800 	lsl	x0, x0, #1
  400934:	8b020000 	add	x0, x0, x2
  400938:	91009000 	add	x0, x0, #0x24
  40093c:	b94463a1 	ldr	w1, [x29, #1120]
  400940:	b8207a61 	str	w1, [x19, x0, lsl #2]
  400944:	b9446ba0 	ldr	w0, [x29, #1128]
  400948:	11000400 	add	w0, w0, #0x1
  40094c:	b9046ba0 	str	w0, [x29, #1128]
  400950:	b9408660 	ldr	w0, [x19, #132]
  400954:	b9446ba1 	ldr	w1, [x29, #1128]
  400958:	6b00003f 	cmp	w1, w0
  40095c:	54fffe0b 	b.lt	40091c <create_1+0x28>  // b.tstop
  400960:	b9446fa0 	ldr	w0, [x29, #1132]
  400964:	11000400 	add	w0, w0, #0x1
  400968:	b9046fa0 	str	w0, [x29, #1132]
  40096c:	b9408660 	ldr	w0, [x19, #132]
  400970:	b9446fa1 	ldr	w1, [x29, #1132]
  400974:	6b00003f 	cmp	w1, w0
  400978:	54fffceb 	b.lt	400914 <create_1+0x20>  // b.tstop
  40097c:	b90467bf 	str	wzr, [x29, #1124]
  400980:	14000017 	b	4009dc <create_1+0xe8>
  400984:	b98467a0 	ldrsw	x0, [x29, #1124]
  400988:	b8607a60 	ldr	w0, [x19, x0, lsl #2]
  40098c:	51000401 	sub	w1, w0, #0x1
  400990:	b98467a0 	ldrsw	x0, [x29, #1124]
  400994:	91002000 	add	x0, x0, #0x8
  400998:	d37ef400 	lsl	x0, x0, #2
  40099c:	8b000260 	add	x0, x19, x0
  4009a0:	b9400800 	ldr	w0, [x0, #8]
  4009a4:	51000400 	sub	w0, w0, #0x1
  4009a8:	93407c02 	sxtw	x2, w0
  4009ac:	93407c21 	sxtw	x1, w1
  4009b0:	aa0103e0 	mov	x0, x1
  4009b4:	d37ef400 	lsl	x0, x0, #2
  4009b8:	8b010000 	add	x0, x0, x1
  4009bc:	d37ff800 	lsl	x0, x0, #1
  4009c0:	8b020000 	add	x0, x0, x2
  4009c4:	91009000 	add	x0, x0, #0x24
  4009c8:	52800021 	mov	w1, #0x1                   	// #1
  4009cc:	b8207a61 	str	w1, [x19, x0, lsl #2]
  4009d0:	b94467a0 	ldr	w0, [x29, #1124]
  4009d4:	11000400 	add	w0, w0, #0x1
  4009d8:	b90467a0 	str	w0, [x29, #1124]
  4009dc:	b9408a60 	ldr	w0, [x19, #136]
  4009e0:	b94467a1 	ldr	w1, [x29, #1124]
  4009e4:	6b00003f 	cmp	w1, w0
  4009e8:	54fffceb 	b.lt	400984 <create_1+0x90>  // b.tstop
  4009ec:	910083a0 	add	x0, x29, #0x20
  4009f0:	aa1303e3 	mov	x3, x19
  4009f4:	d2804401 	mov	x1, #0x220                 	// #544
  4009f8:	aa0103e2 	mov	x2, x1
  4009fc:	aa0303e1 	mov	x1, x3
  400a00:	97ffff0c 	bl	400630 <memcpy@plt>
  400a04:	910083a0 	add	x0, x29, #0x20
  400a08:	910903a1 	add	x1, x29, #0x240
  400a0c:	aa0103e8 	mov	x8, x1
  400a10:	97ffff6f 	bl	4007cc <print_adjmatrix>
  400a14:	d503201f 	nop
  400a18:	f9400bf3 	ldr	x19, [sp, #16]
  400a1c:	a9407bfd 	ldp	x29, x30, [sp]
  400a20:	9111c3ff 	add	sp, sp, #0x470
  400a24:	d65f03c0 	ret

0000000000400a28 <create_2>:
  400a28:	d111c3ff 	sub	sp, sp, #0x470
  400a2c:	a9007bfd 	stp	x29, x30, [sp]
  400a30:	910003fd 	mov	x29, sp
  400a34:	f9000bf3 	str	x19, [sp, #16]
  400a38:	aa0003f3 	mov	x19, x0
  400a3c:	b90463bf 	str	wzr, [x29, #1120]
  400a40:	b9046fbf 	str	wzr, [x29, #1132]
  400a44:	14000017 	b	400aa0 <create_2+0x78>
  400a48:	b9046bbf 	str	wzr, [x29, #1128]
  400a4c:	1400000e 	b	400a84 <create_2+0x5c>
  400a50:	b9846ba2 	ldrsw	x2, [x29, #1128]
  400a54:	b9846fa1 	ldrsw	x1, [x29, #1132]
  400a58:	aa0103e0 	mov	x0, x1
  400a5c:	d37ef400 	lsl	x0, x0, #2
  400a60:	8b010000 	add	x0, x0, x1
  400a64:	d37ff800 	lsl	x0, x0, #1
  400a68:	8b020000 	add	x0, x0, x2
  400a6c:	91009000 	add	x0, x0, #0x24
  400a70:	b94463a1 	ldr	w1, [x29, #1120]
  400a74:	b8207a61 	str	w1, [x19, x0, lsl #2]
  400a78:	b9446ba0 	ldr	w0, [x29, #1128]
  400a7c:	11000400 	add	w0, w0, #0x1
  400a80:	b9046ba0 	str	w0, [x29, #1128]
  400a84:	b9408660 	ldr	w0, [x19, #132]
  400a88:	b9446ba1 	ldr	w1, [x29, #1128]
  400a8c:	6b00003f 	cmp	w1, w0
  400a90:	54fffe0b 	b.lt	400a50 <create_2+0x28>  // b.tstop
  400a94:	b9446fa0 	ldr	w0, [x29, #1132]
  400a98:	11000400 	add	w0, w0, #0x1
  400a9c:	b9046fa0 	str	w0, [x29, #1132]
  400aa0:	b9408660 	ldr	w0, [x19, #132]
  400aa4:	b9446fa1 	ldr	w1, [x29, #1132]
  400aa8:	6b00003f 	cmp	w1, w0
  400aac:	54fffceb 	b.lt	400a48 <create_2+0x20>  // b.tstop
  400ab0:	b90467bf 	str	wzr, [x29, #1124]
  400ab4:	1400002a 	b	400b5c <create_2+0x134>
  400ab8:	b98467a0 	ldrsw	x0, [x29, #1124]
  400abc:	b8607a60 	ldr	w0, [x19, x0, lsl #2]
  400ac0:	51000401 	sub	w1, w0, #0x1
  400ac4:	b98467a0 	ldrsw	x0, [x29, #1124]
  400ac8:	91002000 	add	x0, x0, #0x8
  400acc:	d37ef400 	lsl	x0, x0, #2
  400ad0:	8b000260 	add	x0, x19, x0
  400ad4:	b9400800 	ldr	w0, [x0, #8]
  400ad8:	51000400 	sub	w0, w0, #0x1
  400adc:	93407c02 	sxtw	x2, w0
  400ae0:	93407c21 	sxtw	x1, w1
  400ae4:	aa0103e0 	mov	x0, x1
  400ae8:	d37ef400 	lsl	x0, x0, #2
  400aec:	8b010000 	add	x0, x0, x1
  400af0:	d37ff800 	lsl	x0, x0, #1
  400af4:	8b020000 	add	x0, x0, x2
  400af8:	91009000 	add	x0, x0, #0x24
  400afc:	52800021 	mov	w1, #0x1                   	// #1
  400b00:	b8207a61 	str	w1, [x19, x0, lsl #2]
  400b04:	b98467a0 	ldrsw	x0, [x29, #1124]
  400b08:	91002000 	add	x0, x0, #0x8
  400b0c:	d37ef400 	lsl	x0, x0, #2
  400b10:	8b000260 	add	x0, x19, x0
  400b14:	b9400800 	ldr	w0, [x0, #8]
  400b18:	51000401 	sub	w1, w0, #0x1
  400b1c:	b98467a0 	ldrsw	x0, [x29, #1124]
  400b20:	b8607a60 	ldr	w0, [x19, x0, lsl #2]
  400b24:	51000400 	sub	w0, w0, #0x1
  400b28:	93407c02 	sxtw	x2, w0
  400b2c:	93407c21 	sxtw	x1, w1
  400b30:	aa0103e0 	mov	x0, x1
  400b34:	d37ef400 	lsl	x0, x0, #2
  400b38:	8b010000 	add	x0, x0, x1
  400b3c:	d37ff800 	lsl	x0, x0, #1
  400b40:	8b020000 	add	x0, x0, x2
  400b44:	91009000 	add	x0, x0, #0x24
  400b48:	52800021 	mov	w1, #0x1                   	// #1
  400b4c:	b8207a61 	str	w1, [x19, x0, lsl #2]
  400b50:	b94467a0 	ldr	w0, [x29, #1124]
  400b54:	11000400 	add	w0, w0, #0x1
  400b58:	b90467a0 	str	w0, [x29, #1124]
  400b5c:	b9408a60 	ldr	w0, [x19, #136]
  400b60:	b94467a1 	ldr	w1, [x29, #1124]
  400b64:	6b00003f 	cmp	w1, w0
  400b68:	54fffa8b 	b.lt	400ab8 <create_2+0x90>  // b.tstop
  400b6c:	910083a0 	add	x0, x29, #0x20
  400b70:	aa1303e3 	mov	x3, x19
  400b74:	d2804401 	mov	x1, #0x220                 	// #544
  400b78:	aa0103e2 	mov	x2, x1
  400b7c:	aa0303e1 	mov	x1, x3
  400b80:	97fffeac 	bl	400630 <memcpy@plt>
  400b84:	910083a0 	add	x0, x29, #0x20
  400b88:	910903a1 	add	x1, x29, #0x240
  400b8c:	aa0103e8 	mov	x8, x1
  400b90:	97ffff0f 	bl	4007cc <print_adjmatrix>
  400b94:	d503201f 	nop
  400b98:	f9400bf3 	ldr	x19, [sp, #16]
  400b9c:	a9407bfd 	ldp	x29, x30, [sp]
  400ba0:	9111c3ff 	add	sp, sp, #0x470
  400ba4:	d65f03c0 	ret

0000000000400ba8 <create_3>:
  400ba8:	d111c3ff 	sub	sp, sp, #0x470
  400bac:	a9007bfd 	stp	x29, x30, [sp]
  400bb0:	910003fd 	mov	x29, sp
  400bb4:	a90153f3 	stp	x19, x20, [sp, #16]
  400bb8:	aa0803f4 	mov	x20, x8
  400bbc:	aa0003f3 	mov	x19, x0
  400bc0:	52807ce0 	mov	w0, #0x3e7                 	// #999
  400bc4:	b90463a0 	str	w0, [x29, #1120]
  400bc8:	b9046fbf 	str	wzr, [x29, #1132]
  400bcc:	14000017 	b	400c28 <create_3+0x80>
  400bd0:	b9046bbf 	str	wzr, [x29, #1128]
  400bd4:	1400000e 	b	400c0c <create_3+0x64>
  400bd8:	b9846ba2 	ldrsw	x2, [x29, #1128]
  400bdc:	b9846fa1 	ldrsw	x1, [x29, #1132]
  400be0:	aa0103e0 	mov	x0, x1
  400be4:	d37ef400 	lsl	x0, x0, #2
  400be8:	8b010000 	add	x0, x0, x1
  400bec:	d37ff800 	lsl	x0, x0, #1
  400bf0:	8b020000 	add	x0, x0, x2
  400bf4:	91009000 	add	x0, x0, #0x24
  400bf8:	b94463a1 	ldr	w1, [x29, #1120]
  400bfc:	b8207a61 	str	w1, [x19, x0, lsl #2]
  400c00:	b9446ba0 	ldr	w0, [x29, #1128]
  400c04:	11000400 	add	w0, w0, #0x1
  400c08:	b9046ba0 	str	w0, [x29, #1128]
  400c0c:	b9408660 	ldr	w0, [x19, #132]
  400c10:	b9446ba1 	ldr	w1, [x29, #1128]
  400c14:	6b00003f 	cmp	w1, w0
  400c18:	54fffe0b 	b.lt	400bd8 <create_3+0x30>  // b.tstop
  400c1c:	b9446fa0 	ldr	w0, [x29, #1132]
  400c20:	11000400 	add	w0, w0, #0x1
  400c24:	b9046fa0 	str	w0, [x29, #1132]
  400c28:	b9408660 	ldr	w0, [x19, #132]
  400c2c:	b9446fa1 	ldr	w1, [x29, #1132]
  400c30:	6b00003f 	cmp	w1, w0
  400c34:	54fffceb 	b.lt	400bd0 <create_3+0x28>  // b.tstop
  400c38:	b90467bf 	str	wzr, [x29, #1124]
  400c3c:	14000019 	b	400ca0 <create_3+0xf8>
  400c40:	b98467a0 	ldrsw	x0, [x29, #1124]
  400c44:	b8607a60 	ldr	w0, [x19, x0, lsl #2]
  400c48:	51000401 	sub	w1, w0, #0x1
  400c4c:	b98467a0 	ldrsw	x0, [x29, #1124]
  400c50:	91002000 	add	x0, x0, #0x8
  400c54:	d37ef400 	lsl	x0, x0, #2
  400c58:	8b000260 	add	x0, x19, x0
  400c5c:	b9400800 	ldr	w0, [x0, #8]
  400c60:	51000403 	sub	w3, w0, #0x1
  400c64:	b98467a0 	ldrsw	x0, [x29, #1124]
  400c68:	91005000 	add	x0, x0, #0x14
  400c6c:	b8607a62 	ldr	w2, [x19, x0, lsl #2]
  400c70:	93407c63 	sxtw	x3, w3
  400c74:	93407c21 	sxtw	x1, w1
  400c78:	aa0103e0 	mov	x0, x1
  400c7c:	d37ef400 	lsl	x0, x0, #2
  400c80:	8b010000 	add	x0, x0, x1
  400c84:	d37ff800 	lsl	x0, x0, #1
  400c88:	8b030000 	add	x0, x0, x3
  400c8c:	91009000 	add	x0, x0, #0x24
  400c90:	b8207a62 	str	w2, [x19, x0, lsl #2]
  400c94:	b94467a0 	ldr	w0, [x29, #1124]
  400c98:	11000400 	add	w0, w0, #0x1
  400c9c:	b90467a0 	str	w0, [x29, #1124]
  400ca0:	b9408a60 	ldr	w0, [x19, #136]
  400ca4:	b94467a1 	ldr	w1, [x29, #1124]
  400ca8:	6b00003f 	cmp	w1, w0
  400cac:	54fffcab 	b.lt	400c40 <create_3+0x98>  // b.tstop
  400cb0:	910083a0 	add	x0, x29, #0x20
  400cb4:	aa1303e3 	mov	x3, x19
  400cb8:	d2804401 	mov	x1, #0x220                 	// #544
  400cbc:	aa0103e2 	mov	x2, x1
  400cc0:	aa0303e1 	mov	x1, x3
  400cc4:	97fffe5b 	bl	400630 <memcpy@plt>
  400cc8:	910083a0 	add	x0, x29, #0x20
  400ccc:	910903a1 	add	x1, x29, #0x240
  400cd0:	aa0103e8 	mov	x8, x1
  400cd4:	97fffebe 	bl	4007cc <print_adjmatrix>
  400cd8:	aa1403e3 	mov	x3, x20
  400cdc:	aa1303e1 	mov	x1, x19
  400ce0:	d2804400 	mov	x0, #0x220                 	// #544
  400ce4:	aa0003e2 	mov	x2, x0
  400ce8:	aa0303e0 	mov	x0, x3
  400cec:	97fffe51 	bl	400630 <memcpy@plt>
  400cf0:	a94153f3 	ldp	x19, x20, [sp, #16]
  400cf4:	a9407bfd 	ldp	x29, x30, [sp]
  400cf8:	9111c3ff 	add	sp, sp, #0x470
  400cfc:	d65f03c0 	ret

0000000000400d00 <create_4>:
  400d00:	d111c3ff 	sub	sp, sp, #0x470
  400d04:	a9007bfd 	stp	x29, x30, [sp]
  400d08:	910003fd 	mov	x29, sp
  400d0c:	a90153f3 	stp	x19, x20, [sp, #16]
  400d10:	aa0803f4 	mov	x20, x8
  400d14:	aa0003f3 	mov	x19, x0
  400d18:	52807ce0 	mov	w0, #0x3e7                 	// #999
  400d1c:	b90463a0 	str	w0, [x29, #1120]
  400d20:	b9046fbf 	str	wzr, [x29, #1132]
  400d24:	14000017 	b	400d80 <create_4+0x80>
  400d28:	b9046bbf 	str	wzr, [x29, #1128]
  400d2c:	1400000e 	b	400d64 <create_4+0x64>
  400d30:	b9846ba2 	ldrsw	x2, [x29, #1128]
  400d34:	b9846fa1 	ldrsw	x1, [x29, #1132]
  400d38:	aa0103e0 	mov	x0, x1
  400d3c:	d37ef400 	lsl	x0, x0, #2
  400d40:	8b010000 	add	x0, x0, x1
  400d44:	d37ff800 	lsl	x0, x0, #1
  400d48:	8b020000 	add	x0, x0, x2
  400d4c:	91009000 	add	x0, x0, #0x24
  400d50:	b94463a1 	ldr	w1, [x29, #1120]
  400d54:	b8207a61 	str	w1, [x19, x0, lsl #2]
  400d58:	b9446ba0 	ldr	w0, [x29, #1128]
  400d5c:	11000400 	add	w0, w0, #0x1
  400d60:	b9046ba0 	str	w0, [x29, #1128]
  400d64:	b9408660 	ldr	w0, [x19, #132]
  400d68:	b9446ba1 	ldr	w1, [x29, #1128]
  400d6c:	6b00003f 	cmp	w1, w0
  400d70:	54fffe0b 	b.lt	400d30 <create_4+0x30>  // b.tstop
  400d74:	b9446fa0 	ldr	w0, [x29, #1132]
  400d78:	11000400 	add	w0, w0, #0x1
  400d7c:	b9046fa0 	str	w0, [x29, #1132]
  400d80:	b9408660 	ldr	w0, [x19, #132]
  400d84:	b9446fa1 	ldr	w1, [x29, #1132]
  400d88:	6b00003f 	cmp	w1, w0
  400d8c:	54fffceb 	b.lt	400d28 <create_4+0x28>  // b.tstop
  400d90:	b90467bf 	str	wzr, [x29, #1124]
  400d94:	1400002e 	b	400e4c <create_4+0x14c>
  400d98:	b98467a0 	ldrsw	x0, [x29, #1124]
  400d9c:	b8607a60 	ldr	w0, [x19, x0, lsl #2]
  400da0:	51000401 	sub	w1, w0, #0x1
  400da4:	b98467a0 	ldrsw	x0, [x29, #1124]
  400da8:	91002000 	add	x0, x0, #0x8
  400dac:	d37ef400 	lsl	x0, x0, #2
  400db0:	8b000260 	add	x0, x19, x0
  400db4:	b9400800 	ldr	w0, [x0, #8]
  400db8:	51000403 	sub	w3, w0, #0x1
  400dbc:	b98467a0 	ldrsw	x0, [x29, #1124]
  400dc0:	91005000 	add	x0, x0, #0x14
  400dc4:	b8607a62 	ldr	w2, [x19, x0, lsl #2]
  400dc8:	93407c63 	sxtw	x3, w3
  400dcc:	93407c21 	sxtw	x1, w1
  400dd0:	aa0103e0 	mov	x0, x1
  400dd4:	d37ef400 	lsl	x0, x0, #2
  400dd8:	8b010000 	add	x0, x0, x1
  400ddc:	d37ff800 	lsl	x0, x0, #1
  400de0:	8b030000 	add	x0, x0, x3
  400de4:	91009000 	add	x0, x0, #0x24
  400de8:	b8207a62 	str	w2, [x19, x0, lsl #2]
  400dec:	b98467a0 	ldrsw	x0, [x29, #1124]
  400df0:	91002000 	add	x0, x0, #0x8
  400df4:	d37ef400 	lsl	x0, x0, #2
  400df8:	8b000260 	add	x0, x19, x0
  400dfc:	b9400800 	ldr	w0, [x0, #8]
  400e00:	51000401 	sub	w1, w0, #0x1
  400e04:	b98467a0 	ldrsw	x0, [x29, #1124]
  400e08:	b8607a60 	ldr	w0, [x19, x0, lsl #2]
  400e0c:	51000403 	sub	w3, w0, #0x1
  400e10:	b98467a0 	ldrsw	x0, [x29, #1124]
  400e14:	91005000 	add	x0, x0, #0x14
  400e18:	b8607a62 	ldr	w2, [x19, x0, lsl #2]
  400e1c:	93407c63 	sxtw	x3, w3
  400e20:	93407c21 	sxtw	x1, w1
  400e24:	aa0103e0 	mov	x0, x1
  400e28:	d37ef400 	lsl	x0, x0, #2
  400e2c:	8b010000 	add	x0, x0, x1
  400e30:	d37ff800 	lsl	x0, x0, #1
  400e34:	8b030000 	add	x0, x0, x3
  400e38:	91009000 	add	x0, x0, #0x24
  400e3c:	b8207a62 	str	w2, [x19, x0, lsl #2]
  400e40:	b94467a0 	ldr	w0, [x29, #1124]
  400e44:	11000400 	add	w0, w0, #0x1
  400e48:	b90467a0 	str	w0, [x29, #1124]
  400e4c:	b9408a60 	ldr	w0, [x19, #136]
  400e50:	b94467a1 	ldr	w1, [x29, #1124]
  400e54:	6b00003f 	cmp	w1, w0
  400e58:	54fffa0b 	b.lt	400d98 <create_4+0x98>  // b.tstop
  400e5c:	910083a0 	add	x0, x29, #0x20
  400e60:	aa1303e3 	mov	x3, x19
  400e64:	d2804401 	mov	x1, #0x220                 	// #544
  400e68:	aa0103e2 	mov	x2, x1
  400e6c:	aa0303e1 	mov	x1, x3
  400e70:	97fffdf0 	bl	400630 <memcpy@plt>
  400e74:	910083a0 	add	x0, x29, #0x20
  400e78:	910903a1 	add	x1, x29, #0x240
  400e7c:	aa0103e8 	mov	x8, x1
  400e80:	97fffe53 	bl	4007cc <print_adjmatrix>
  400e84:	aa1403e3 	mov	x3, x20
  400e88:	aa1303e1 	mov	x1, x19
  400e8c:	d2804400 	mov	x0, #0x220                 	// #544
  400e90:	aa0003e2 	mov	x2, x0
  400e94:	aa0303e0 	mov	x0, x3
  400e98:	97fffde6 	bl	400630 <memcpy@plt>
  400e9c:	a94153f3 	ldp	x19, x20, [sp, #16]
  400ea0:	a9407bfd 	ldp	x29, x30, [sp]
  400ea4:	9111c3ff 	add	sp, sp, #0x470
  400ea8:	d65f03c0 	ret

0000000000400eac <creategraph>:
  400eac:	d11183ff 	sub	sp, sp, #0x460
  400eb0:	a9007bfd 	stp	x29, x30, [sp]
  400eb4:	910003fd 	mov	x29, sp
  400eb8:	f9000bf3 	str	x19, [sp, #16]
  400ebc:	aa0003f3 	mov	x19, x0
  400ec0:	b9408e60 	ldr	w0, [x19, #140]
  400ec4:	7100081f 	cmp	w0, #0x2
  400ec8:	54000280 	b.eq	400f18 <creategraph+0x6c>  // b.none
  400ecc:	7100081f 	cmp	w0, #0x2
  400ed0:	5400008c 	b.gt	400ee0 <creategraph+0x34>
  400ed4:	7100041f 	cmp	w0, #0x1
  400ed8:	540000e0 	b.eq	400ef4 <creategraph+0x48>  // b.none
  400edc:	1400002e 	b	400f94 <creategraph+0xe8>
  400ee0:	71000c1f 	cmp	w0, #0x3
  400ee4:	540002c0 	b.eq	400f3c <creategraph+0x90>  // b.none
  400ee8:	7100101f 	cmp	w0, #0x4
  400eec:	540003e0 	b.eq	400f68 <creategraph+0xbc>  // b.none
  400ef0:	14000029 	b	400f94 <creategraph+0xe8>
  400ef4:	910903a0 	add	x0, x29, #0x240
  400ef8:	aa1303e3 	mov	x3, x19
  400efc:	d2804401 	mov	x1, #0x220                 	// #544
  400f00:	aa0103e2 	mov	x2, x1
  400f04:	aa0303e1 	mov	x1, x3
  400f08:	97fffdca 	bl	400630 <memcpy@plt>
  400f0c:	910903a0 	add	x0, x29, #0x240
  400f10:	97fffe79 	bl	4008f4 <create_1>
  400f14:	14000023 	b	400fa0 <creategraph+0xf4>
  400f18:	910903a0 	add	x0, x29, #0x240
  400f1c:	aa1303e3 	mov	x3, x19
  400f20:	d2804401 	mov	x1, #0x220                 	// #544
  400f24:	aa0103e2 	mov	x2, x1
  400f28:	aa0303e1 	mov	x1, x3
  400f2c:	97fffdc1 	bl	400630 <memcpy@plt>
  400f30:	910903a0 	add	x0, x29, #0x240
  400f34:	97fffebd 	bl	400a28 <create_2>
  400f38:	1400001a 	b	400fa0 <creategraph+0xf4>
  400f3c:	910083a0 	add	x0, x29, #0x20
  400f40:	aa1303e3 	mov	x3, x19
  400f44:	d2804401 	mov	x1, #0x220                 	// #544
  400f48:	aa0103e2 	mov	x2, x1
  400f4c:	aa0303e1 	mov	x1, x3
  400f50:	97fffdb8 	bl	400630 <memcpy@plt>
  400f54:	910083a0 	add	x0, x29, #0x20
  400f58:	910903a1 	add	x1, x29, #0x240
  400f5c:	aa0103e8 	mov	x8, x1
  400f60:	97ffff12 	bl	400ba8 <create_3>
  400f64:	1400000f 	b	400fa0 <creategraph+0xf4>
  400f68:	910903a0 	add	x0, x29, #0x240
  400f6c:	aa1303e3 	mov	x3, x19
  400f70:	d2804401 	mov	x1, #0x220                 	// #544
  400f74:	aa0103e2 	mov	x2, x1
  400f78:	aa0303e1 	mov	x1, x3
  400f7c:	97fffdad 	bl	400630 <memcpy@plt>
  400f80:	910903a0 	add	x0, x29, #0x240
  400f84:	910083a1 	add	x1, x29, #0x20
  400f88:	aa0103e8 	mov	x8, x1
  400f8c:	97ffff5d 	bl	400d00 <create_4>
  400f90:	14000004 	b	400fa0 <creategraph+0xf4>
  400f94:	f0000000 	adrp	x0, 403000 <main+0x790>
  400f98:	910a2000 	add	x0, x0, #0x288
  400f9c:	97fffdb9 	bl	400680 <puts@plt>
  400fa0:	d503201f 	nop
  400fa4:	f9400bf3 	ldr	x19, [sp, #16]
  400fa8:	a9407bfd 	ldp	x29, x30, [sp]
  400fac:	911183ff 	add	sp, sp, #0x460
  400fb0:	d65f03c0 	ret

0000000000400fb4 <createlist>:
  400fb4:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400fb8:	910003fd 	mov	x29, sp
  400fbc:	a90153f3 	stp	x19, x20, [sp, #16]
  400fc0:	f90013f5 	str	x21, [sp, #32]
  400fc4:	aa0803f5 	mov	x21, x8
  400fc8:	aa0003f3 	mov	x19, x0
  400fcc:	aa0103f4 	mov	x20, x1
  400fd0:	b9408e60 	ldr	w0, [x19, #140]
  400fd4:	7100041f 	cmp	w0, #0x1
  400fd8:	54000080 	b.eq	400fe8 <createlist+0x34>  // b.none
  400fdc:	b9408e60 	ldr	w0, [x19, #140]
  400fe0:	71000c1f 	cmp	w0, #0x3
  400fe4:	54000541 	b.ne	40108c <createlist+0xd8>  // b.any
  400fe8:	b9003fbf 	str	wzr, [x29, #60]
  400fec:	14000024 	b	40107c <createlist+0xc8>
  400ff0:	d2800200 	mov	x0, #0x10                  	// #16
  400ff4:	97fffd93 	bl	400640 <malloc@plt>
  400ff8:	f9001ba0 	str	x0, [x29, #48]
  400ffc:	b9803fa0 	ldrsw	x0, [x29, #60]
  401000:	91002000 	add	x0, x0, #0x8
  401004:	d37ef400 	lsl	x0, x0, #2
  401008:	8b000260 	add	x0, x19, x0
  40100c:	b9400801 	ldr	w1, [x0, #8]
  401010:	f9401ba0 	ldr	x0, [x29, #48]
  401014:	b9000001 	str	w1, [x0]
  401018:	b9803fa0 	ldrsw	x0, [x29, #60]
  40101c:	91005000 	add	x0, x0, #0x14
  401020:	b8607a61 	ldr	w1, [x19, x0, lsl #2]
  401024:	f9401ba0 	ldr	x0, [x29, #48]
  401028:	b9000401 	str	w1, [x0, #4]
  40102c:	b9803fa0 	ldrsw	x0, [x29, #60]
  401030:	b8607a60 	ldr	w0, [x19, x0, lsl #2]
  401034:	51000400 	sub	w0, w0, #0x1
  401038:	93407c00 	sxtw	x0, w0
  40103c:	d37cec00 	lsl	x0, x0, #4
  401040:	8b000280 	add	x0, x20, x0
  401044:	f9400401 	ldr	x1, [x0, #8]
  401048:	f9401ba0 	ldr	x0, [x29, #48]
  40104c:	f9000401 	str	x1, [x0, #8]
  401050:	b9803fa0 	ldrsw	x0, [x29, #60]
  401054:	b8607a60 	ldr	w0, [x19, x0, lsl #2]
  401058:	51000400 	sub	w0, w0, #0x1
  40105c:	93407c00 	sxtw	x0, w0
  401060:	d37cec00 	lsl	x0, x0, #4
  401064:	8b000280 	add	x0, x20, x0
  401068:	f9401ba1 	ldr	x1, [x29, #48]
  40106c:	f9000401 	str	x1, [x0, #8]
  401070:	b9403fa0 	ldr	w0, [x29, #60]
  401074:	11000400 	add	w0, w0, #0x1
  401078:	b9003fa0 	str	w0, [x29, #60]
  40107c:	b940a680 	ldr	w0, [x20, #164]
  401080:	b9403fa1 	ldr	w1, [x29, #60]
  401084:	6b00003f 	cmp	w1, w0
  401088:	54fffb4b 	b.lt	400ff0 <createlist+0x3c>  // b.tstop
  40108c:	b9408e60 	ldr	w0, [x19, #140]
  401090:	7100081f 	cmp	w0, #0x2
  401094:	54000080 	b.eq	4010a4 <createlist+0xf0>  // b.none
  401098:	b9408e60 	ldr	w0, [x19, #140]
  40109c:	7100101f 	cmp	w0, #0x4
  4010a0:	540009a1 	b.ne	4011d4 <createlist+0x220>  // b.any
  4010a4:	b9003fbf 	str	wzr, [x29, #60]
  4010a8:	14000047 	b	4011c4 <createlist+0x210>
  4010ac:	d2800200 	mov	x0, #0x10                  	// #16
  4010b0:	97fffd64 	bl	400640 <malloc@plt>
  4010b4:	f9001ba0 	str	x0, [x29, #48]
  4010b8:	b9803fa0 	ldrsw	x0, [x29, #60]
  4010bc:	91005000 	add	x0, x0, #0x14
  4010c0:	b8607a61 	ldr	w1, [x19, x0, lsl #2]
  4010c4:	f9401ba0 	ldr	x0, [x29, #48]
  4010c8:	b9000401 	str	w1, [x0, #4]
  4010cc:	b9803fa0 	ldrsw	x0, [x29, #60]
  4010d0:	91002000 	add	x0, x0, #0x8
  4010d4:	d37ef400 	lsl	x0, x0, #2
  4010d8:	8b000260 	add	x0, x19, x0
  4010dc:	b9400801 	ldr	w1, [x0, #8]
  4010e0:	f9401ba0 	ldr	x0, [x29, #48]
  4010e4:	b9000001 	str	w1, [x0]
  4010e8:	b9803fa0 	ldrsw	x0, [x29, #60]
  4010ec:	b8607a60 	ldr	w0, [x19, x0, lsl #2]
  4010f0:	51000400 	sub	w0, w0, #0x1
  4010f4:	93407c00 	sxtw	x0, w0
  4010f8:	d37cec00 	lsl	x0, x0, #4
  4010fc:	8b000280 	add	x0, x20, x0
  401100:	f9400401 	ldr	x1, [x0, #8]
  401104:	f9401ba0 	ldr	x0, [x29, #48]
  401108:	f9000401 	str	x1, [x0, #8]
  40110c:	b9803fa0 	ldrsw	x0, [x29, #60]
  401110:	b8607a60 	ldr	w0, [x19, x0, lsl #2]
  401114:	51000400 	sub	w0, w0, #0x1
  401118:	93407c00 	sxtw	x0, w0
  40111c:	d37cec00 	lsl	x0, x0, #4
  401120:	8b000280 	add	x0, x20, x0
  401124:	f9401ba1 	ldr	x1, [x29, #48]
  401128:	f9000401 	str	x1, [x0, #8]
  40112c:	d2800200 	mov	x0, #0x10                  	// #16
  401130:	97fffd44 	bl	400640 <malloc@plt>
  401134:	f9001ba0 	str	x0, [x29, #48]
  401138:	b9803fa0 	ldrsw	x0, [x29, #60]
  40113c:	91005000 	add	x0, x0, #0x14
  401140:	b8607a61 	ldr	w1, [x19, x0, lsl #2]
  401144:	f9401ba0 	ldr	x0, [x29, #48]
  401148:	b9000401 	str	w1, [x0, #4]
  40114c:	b9803fa0 	ldrsw	x0, [x29, #60]
  401150:	b8607a61 	ldr	w1, [x19, x0, lsl #2]
  401154:	f9401ba0 	ldr	x0, [x29, #48]
  401158:	b9000001 	str	w1, [x0]
  40115c:	b9803fa0 	ldrsw	x0, [x29, #60]
  401160:	91002000 	add	x0, x0, #0x8
  401164:	d37ef400 	lsl	x0, x0, #2
  401168:	8b000260 	add	x0, x19, x0
  40116c:	b9400800 	ldr	w0, [x0, #8]
  401170:	51000400 	sub	w0, w0, #0x1
  401174:	93407c00 	sxtw	x0, w0
  401178:	d37cec00 	lsl	x0, x0, #4
  40117c:	8b000280 	add	x0, x20, x0
  401180:	f9400401 	ldr	x1, [x0, #8]
  401184:	f9401ba0 	ldr	x0, [x29, #48]
  401188:	f9000401 	str	x1, [x0, #8]
  40118c:	b9803fa0 	ldrsw	x0, [x29, #60]
  401190:	91002000 	add	x0, x0, #0x8
  401194:	d37ef400 	lsl	x0, x0, #2
  401198:	8b000260 	add	x0, x19, x0
  40119c:	b9400800 	ldr	w0, [x0, #8]
  4011a0:	51000400 	sub	w0, w0, #0x1
  4011a4:	93407c00 	sxtw	x0, w0
  4011a8:	d37cec00 	lsl	x0, x0, #4
  4011ac:	8b000280 	add	x0, x20, x0
  4011b0:	f9401ba1 	ldr	x1, [x29, #48]
  4011b4:	f9000401 	str	x1, [x0, #8]
  4011b8:	b9403fa0 	ldr	w0, [x29, #60]
  4011bc:	11000400 	add	w0, w0, #0x1
  4011c0:	b9003fa0 	str	w0, [x29, #60]
  4011c4:	b940a680 	ldr	w0, [x20, #164]
  4011c8:	b9403fa1 	ldr	w1, [x29, #60]
  4011cc:	6b00003f 	cmp	w1, w0
  4011d0:	54fff6eb 	b.lt	4010ac <createlist+0xf8>  // b.tstop
  4011d4:	d0000000 	adrp	x0, 403000 <main+0x790>
  4011d8:	910a4000 	add	x0, x0, #0x290
  4011dc:	97fffd29 	bl	400680 <puts@plt>
  4011e0:	b9003fbf 	str	wzr, [x29, #60]
  4011e4:	1400002b 	b	401290 <createlist+0x2dc>
  4011e8:	b9403fa0 	ldr	w0, [x29, #60]
  4011ec:	11000401 	add	w1, w0, #0x1
  4011f0:	b9803fa0 	ldrsw	x0, [x29, #60]
  4011f4:	d37cec00 	lsl	x0, x0, #4
  4011f8:	8b000280 	add	x0, x20, x0
  4011fc:	39401000 	ldrb	w0, [x0, #4]
  401200:	2a0003e2 	mov	w2, w0
  401204:	d0000000 	adrp	x0, 403000 <main+0x790>
  401208:	910aa000 	add	x0, x0, #0x2a8
  40120c:	97fffd29 	bl	4006b0 <printf@plt>
  401210:	b9803fa0 	ldrsw	x0, [x29, #60]
  401214:	d37cec00 	lsl	x0, x0, #4
  401218:	8b000280 	add	x0, x20, x0
  40121c:	f9400400 	ldr	x0, [x0, #8]
  401220:	f9001ba0 	str	x0, [x29, #48]
  401224:	14000013 	b	401270 <createlist+0x2bc>
  401228:	f9401ba0 	ldr	x0, [x29, #48]
  40122c:	b9400000 	ldr	w0, [x0]
  401230:	51000400 	sub	w0, w0, #0x1
  401234:	93407c00 	sxtw	x0, w0
  401238:	d37cec00 	lsl	x0, x0, #4
  40123c:	8b000280 	add	x0, x20, x0
  401240:	39401000 	ldrb	w0, [x0, #4]
  401244:	2a0003e3 	mov	w3, w0
  401248:	f9401ba0 	ldr	x0, [x29, #48]
  40124c:	b9400401 	ldr	w1, [x0, #4]
  401250:	d0000000 	adrp	x0, 403000 <main+0x790>
  401254:	910ae000 	add	x0, x0, #0x2b8
  401258:	2a0103e2 	mov	w2, w1
  40125c:	2a0303e1 	mov	w1, w3
  401260:	97fffd14 	bl	4006b0 <printf@plt>
  401264:	f9401ba0 	ldr	x0, [x29, #48]
  401268:	f9400400 	ldr	x0, [x0, #8]
  40126c:	f9001ba0 	str	x0, [x29, #48]
  401270:	f9401ba0 	ldr	x0, [x29, #48]
  401274:	f100001f 	cmp	x0, #0x0
  401278:	54fffd81 	b.ne	401228 <createlist+0x274>  // b.any
  40127c:	52800140 	mov	w0, #0xa                   	// #10
  401280:	97fffd10 	bl	4006c0 <putchar@plt>
  401284:	b9403fa0 	ldr	w0, [x29, #60]
  401288:	11000400 	add	w0, w0, #0x1
  40128c:	b9003fa0 	str	w0, [x29, #60]
  401290:	b9408660 	ldr	w0, [x19, #132]
  401294:	b9403fa1 	ldr	w1, [x29, #60]
  401298:	6b00003f 	cmp	w1, w0
  40129c:	54fffa6b 	b.lt	4011e8 <createlist+0x234>  // b.tstop
  4012a0:	aa1503e3 	mov	x3, x21
  4012a4:	aa1403e1 	mov	x1, x20
  4012a8:	d2801600 	mov	x0, #0xb0                  	// #176
  4012ac:	aa0003e2 	mov	x2, x0
  4012b0:	aa0303e0 	mov	x0, x3
  4012b4:	97fffcdf 	bl	400630 <memcpy@plt>
  4012b8:	a94153f3 	ldp	x19, x20, [sp, #16]
  4012bc:	f94013f5 	ldr	x21, [sp, #32]
  4012c0:	a8c47bfd 	ldp	x29, x30, [sp], #64
  4012c4:	d65f03c0 	ret

00000000004012c8 <initqueue>:
  4012c8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4012cc:	910003fd 	mov	x29, sp
  4012d0:	f9000fa0 	str	x0, [x29, #24]
  4012d4:	d2800200 	mov	x0, #0x10                  	// #16
  4012d8:	97fffcda 	bl	400640 <malloc@plt>
  4012dc:	aa0003e1 	mov	x1, x0
  4012e0:	f9400fa0 	ldr	x0, [x29, #24]
  4012e4:	f9000001 	str	x1, [x0]
  4012e8:	f9400fa0 	ldr	x0, [x29, #24]
  4012ec:	f9400001 	ldr	x1, [x0]
  4012f0:	f9400fa0 	ldr	x0, [x29, #24]
  4012f4:	f9000401 	str	x1, [x0, #8]
  4012f8:	f9400fa0 	ldr	x0, [x29, #24]
  4012fc:	f9400000 	ldr	x0, [x0]
  401300:	f900041f 	str	xzr, [x0, #8]
  401304:	d503201f 	nop
  401308:	a8c27bfd 	ldp	x29, x30, [sp], #32
  40130c:	d65f03c0 	ret

0000000000401310 <empty>:
  401310:	d10083ff 	sub	sp, sp, #0x20
  401314:	f90007e0 	str	x0, [sp, #8]
  401318:	f94007e0 	ldr	x0, [sp, #8]
  40131c:	f9400001 	ldr	x1, [x0]
  401320:	f94007e0 	ldr	x0, [sp, #8]
  401324:	f9400400 	ldr	x0, [x0, #8]
  401328:	eb00003f 	cmp	x1, x0
  40132c:	54000081 	b.ne	40133c <empty+0x2c>  // b.any
  401330:	52800020 	mov	w0, #0x1                   	// #1
  401334:	b9001fe0 	str	w0, [sp, #28]
  401338:	14000002 	b	401340 <empty+0x30>
  40133c:	b9001fff 	str	wzr, [sp, #28]
  401340:	b9401fe0 	ldr	w0, [sp, #28]
  401344:	910083ff 	add	sp, sp, #0x20
  401348:	d65f03c0 	ret

000000000040134c <addqueue>:
  40134c:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  401350:	910003fd 	mov	x29, sp
  401354:	f9000bf3 	str	x19, [sp, #16]
  401358:	f90017a0 	str	x0, [x29, #40]
  40135c:	b90027a1 	str	w1, [x29, #36]
  401360:	f94017a0 	ldr	x0, [x29, #40]
  401364:	f9400413 	ldr	x19, [x0, #8]
  401368:	d2800200 	mov	x0, #0x10                  	// #16
  40136c:	97fffcb5 	bl	400640 <malloc@plt>
  401370:	f9000660 	str	x0, [x19, #8]
  401374:	f94017a0 	ldr	x0, [x29, #40]
  401378:	f9400400 	ldr	x0, [x0, #8]
  40137c:	f9400401 	ldr	x1, [x0, #8]
  401380:	f94017a0 	ldr	x0, [x29, #40]
  401384:	f9000401 	str	x1, [x0, #8]
  401388:	f94017a0 	ldr	x0, [x29, #40]
  40138c:	f9400400 	ldr	x0, [x0, #8]
  401390:	f100001f 	cmp	x0, #0x0
  401394:	54000061 	b.ne	4013a0 <addqueue+0x54>  // b.any
  401398:	12800000 	mov	w0, #0xffffffff            	// #-1
  40139c:	14000009 	b	4013c0 <addqueue+0x74>
  4013a0:	f94017a0 	ldr	x0, [x29, #40]
  4013a4:	f9400400 	ldr	x0, [x0, #8]
  4013a8:	b94027a1 	ldr	w1, [x29, #36]
  4013ac:	b9000001 	str	w1, [x0]
  4013b0:	f94017a0 	ldr	x0, [x29, #40]
  4013b4:	f9400400 	ldr	x0, [x0, #8]
  4013b8:	f900041f 	str	xzr, [x0, #8]
  4013bc:	52800000 	mov	w0, #0x0                   	// #0
  4013c0:	f9400bf3 	ldr	x19, [sp, #16]
  4013c4:	a8c37bfd 	ldp	x29, x30, [sp], #48
  4013c8:	d65f03c0 	ret

00000000004013cc <delqueue>:
  4013cc:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4013d0:	910003fd 	mov	x29, sp
  4013d4:	f9000fa0 	str	x0, [x29, #24]
  4013d8:	f9400fa0 	ldr	x0, [x29, #24]
  4013dc:	f9400001 	ldr	x1, [x0]
  4013e0:	f9400fa0 	ldr	x0, [x29, #24]
  4013e4:	f9400400 	ldr	x0, [x0, #8]
  4013e8:	eb00003f 	cmp	x1, x0
  4013ec:	540000a1 	b.ne	401400 <delqueue+0x34>  // b.any
  4013f0:	d0000000 	adrp	x0, 403000 <main+0x790>
  4013f4:	910b2000 	add	x0, x0, #0x2c8
  4013f8:	97fffca2 	bl	400680 <puts@plt>
  4013fc:	14000005 	b	401410 <delqueue+0x44>
  401400:	f9400fa0 	ldr	x0, [x29, #24]
  401404:	f9400000 	ldr	x0, [x0]
  401408:	f9400400 	ldr	x0, [x0, #8]
  40140c:	f90017a0 	str	x0, [x29, #40]
  401410:	f9400fa0 	ldr	x0, [x29, #24]
  401414:	f9400000 	ldr	x0, [x0]
  401418:	f94017a1 	ldr	x1, [x29, #40]
  40141c:	f9400421 	ldr	x1, [x1, #8]
  401420:	f9000401 	str	x1, [x0, #8]
  401424:	f94017a0 	ldr	x0, [x29, #40]
  401428:	b9400000 	ldr	w0, [x0]
  40142c:	b90027a0 	str	w0, [x29, #36]
  401430:	f9400fa0 	ldr	x0, [x29, #24]
  401434:	f9400400 	ldr	x0, [x0, #8]
  401438:	f94017a1 	ldr	x1, [x29, #40]
  40143c:	eb00003f 	cmp	x1, x0
  401440:	540000a1 	b.ne	401454 <delqueue+0x88>  // b.any
  401444:	f9400fa0 	ldr	x0, [x29, #24]
  401448:	f9400001 	ldr	x1, [x0]
  40144c:	f9400fa0 	ldr	x0, [x29, #24]
  401450:	f9000401 	str	x1, [x0, #8]
  401454:	f94017a0 	ldr	x0, [x29, #40]
  401458:	97fffc8e 	bl	400690 <free@plt>
  40145c:	b94027a0 	ldr	w0, [x29, #36]
  401460:	a8c37bfd 	ldp	x29, x30, [sp], #48
  401464:	d65f03c0 	ret

0000000000401468 <dfs>:
  401468:	a9ae7bfd 	stp	x29, x30, [sp, #-288]!
  40146c:	910003fd 	mov	x29, sp
  401470:	a90153f3 	stp	x19, x20, [sp, #16]
  401474:	b900dfa0 	str	w0, [x29, #220]
  401478:	aa0103f3 	mov	x19, x1
  40147c:	b90117bf 	str	wzr, [x29, #276]
  401480:	14000008 	b	4014a0 <dfs+0x38>
  401484:	b98117a0 	ldrsw	x0, [x29, #276]
  401488:	d37ef400 	lsl	x0, x0, #2
  40148c:	9103a3a1 	add	x1, x29, #0xe8
  401490:	b820683f 	str	wzr, [x1, x0]
  401494:	b94117a0 	ldr	w0, [x29, #276]
  401498:	11000400 	add	w0, w0, #0x1
  40149c:	b90117a0 	str	w0, [x29, #276]
  4014a0:	b940a260 	ldr	w0, [x19, #160]
  4014a4:	b94117a1 	ldr	w1, [x29, #276]
  4014a8:	6b00003f 	cmp	w1, w0
  4014ac:	54fffecb 	b.lt	401484 <dfs+0x1c>  // b.tstop
  4014b0:	b940dfa0 	ldr	w0, [x29, #220]
  4014b4:	51000400 	sub	w0, w0, #0x1
  4014b8:	93407c00 	sxtw	x0, w0
  4014bc:	d37cec00 	lsl	x0, x0, #4
  4014c0:	8b000260 	add	x0, x19, x0
  4014c4:	39401000 	ldrb	w0, [x0, #4]
  4014c8:	2a0003e1 	mov	w1, w0
  4014cc:	d0000000 	adrp	x0, 403000 <main+0x790>
  4014d0:	910ba000 	add	x0, x0, #0x2e8
  4014d4:	97fffc77 	bl	4006b0 <printf@plt>
  4014d8:	b940dfa0 	ldr	w0, [x29, #220]
  4014dc:	51000400 	sub	w0, w0, #0x1
  4014e0:	93407c00 	sxtw	x0, w0
  4014e4:	d37ef400 	lsl	x0, x0, #2
  4014e8:	9103a3a1 	add	x1, x29, #0xe8
  4014ec:	52800022 	mov	w2, #0x1                   	// #1
  4014f0:	b8206822 	str	w2, [x1, x0]
  4014f4:	b940dfa0 	ldr	w0, [x29, #220]
  4014f8:	51000400 	sub	w0, w0, #0x1
  4014fc:	93407c00 	sxtw	x0, w0
  401500:	d37cec00 	lsl	x0, x0, #4
  401504:	8b000260 	add	x0, x19, x0
  401508:	f9400400 	ldr	x0, [x0, #8]
  40150c:	f9008fa0 	str	x0, [x29, #280]
  401510:	14000019 	b	401574 <dfs+0x10c>
  401514:	f9408fa0 	ldr	x0, [x29, #280]
  401518:	b9400000 	ldr	w0, [x0]
  40151c:	51000400 	sub	w0, w0, #0x1
  401520:	93407c00 	sxtw	x0, w0
  401524:	d37ef400 	lsl	x0, x0, #2
  401528:	9103a3a1 	add	x1, x29, #0xe8
  40152c:	b8606820 	ldr	w0, [x1, x0]
  401530:	7100041f 	cmp	w0, #0x1
  401534:	540001a0 	b.eq	401568 <dfs+0x100>  // b.none
  401538:	f9408fa0 	ldr	x0, [x29, #280]
  40153c:	b9400014 	ldr	w20, [x0]
  401540:	910083a0 	add	x0, x29, #0x20
  401544:	aa1303e3 	mov	x3, x19
  401548:	d2801601 	mov	x1, #0xb0                  	// #176
  40154c:	aa0103e2 	mov	x2, x1
  401550:	aa0303e1 	mov	x1, x3
  401554:	97fffc37 	bl	400630 <memcpy@plt>
  401558:	910083a0 	add	x0, x29, #0x20
  40155c:	aa0003e1 	mov	x1, x0
  401560:	2a1403e0 	mov	w0, w20
  401564:	97ffffc1 	bl	401468 <dfs>
  401568:	f9408fa0 	ldr	x0, [x29, #280]
  40156c:	f9400400 	ldr	x0, [x0, #8]
  401570:	f9008fa0 	str	x0, [x29, #280]
  401574:	f9408fa0 	ldr	x0, [x29, #280]
  401578:	f100001f 	cmp	x0, #0x0
  40157c:	54fffcc1 	b.ne	401514 <dfs+0xac>  // b.any
  401580:	d503201f 	nop
  401584:	a94153f3 	ldp	x19, x20, [sp, #16]
  401588:	a8d27bfd 	ldp	x29, x30, [sp], #288
  40158c:	d65f03c0 	ret

0000000000401590 <bfs>:
  401590:	a9b97bfd 	stp	x29, x30, [sp, #-112]!
  401594:	910003fd 	mov	x29, sp
  401598:	f9000bf3 	str	x19, [sp, #16]
  40159c:	b9002fa0 	str	w0, [x29, #44]
  4015a0:	aa0103f3 	mov	x19, x1
  4015a4:	b90067bf 	str	wzr, [x29, #100]
  4015a8:	14000008 	b	4015c8 <bfs+0x38>
  4015ac:	b98067a0 	ldrsw	x0, [x29, #100]
  4015b0:	d37ef400 	lsl	x0, x0, #2
  4015b4:	9100e3a1 	add	x1, x29, #0x38
  4015b8:	b820683f 	str	wzr, [x1, x0]
  4015bc:	b94067a0 	ldr	w0, [x29, #100]
  4015c0:	11000400 	add	w0, w0, #0x1
  4015c4:	b90067a0 	str	w0, [x29, #100]
  4015c8:	b940a260 	ldr	w0, [x19, #160]
  4015cc:	b94067a1 	ldr	w1, [x29, #100]
  4015d0:	6b00003f 	cmp	w1, w0
  4015d4:	54fffecb 	b.lt	4015ac <bfs+0x1c>  // b.tstop
  4015d8:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  4015dc:	910bc000 	add	x0, x0, #0x2f0
  4015e0:	f9400000 	ldr	x0, [x0]
  4015e4:	97ffff39 	bl	4012c8 <initqueue>
  4015e8:	b9402fa0 	ldr	w0, [x29, #44]
  4015ec:	51000400 	sub	w0, w0, #0x1
  4015f0:	93407c00 	sxtw	x0, w0
  4015f4:	d37cec00 	lsl	x0, x0, #4
  4015f8:	8b000260 	add	x0, x19, x0
  4015fc:	39401000 	ldrb	w0, [x0, #4]
  401600:	2a0003e1 	mov	w1, w0
  401604:	d0000000 	adrp	x0, 403000 <main+0x790>
  401608:	910ba000 	add	x0, x0, #0x2e8
  40160c:	97fffc29 	bl	4006b0 <printf@plt>
  401610:	b9402fa0 	ldr	w0, [x29, #44]
  401614:	51000400 	sub	w0, w0, #0x1
  401618:	93407c00 	sxtw	x0, w0
  40161c:	d37ef400 	lsl	x0, x0, #2
  401620:	9100e3a1 	add	x1, x29, #0x38
  401624:	52800022 	mov	w2, #0x1                   	// #1
  401628:	b8206822 	str	w2, [x1, x0]
  40162c:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  401630:	910bc000 	add	x0, x0, #0x2f0
  401634:	f9400000 	ldr	x0, [x0]
  401638:	b9402fa1 	ldr	w1, [x29, #44]
  40163c:	97ffff44 	bl	40134c <addqueue>
  401640:	14000038 	b	401720 <bfs+0x190>
  401644:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  401648:	910bc000 	add	x0, x0, #0x2f0
  40164c:	f9400000 	ldr	x0, [x0]
  401650:	97ffff5f 	bl	4013cc <delqueue>
  401654:	b9002fa0 	str	w0, [x29, #44]
  401658:	b9402fa0 	ldr	w0, [x29, #44]
  40165c:	51000400 	sub	w0, w0, #0x1
  401660:	93407c00 	sxtw	x0, w0
  401664:	d37cec00 	lsl	x0, x0, #4
  401668:	8b000260 	add	x0, x19, x0
  40166c:	f9400400 	ldr	x0, [x0, #8]
  401670:	f90037a0 	str	x0, [x29, #104]
  401674:	14000028 	b	401714 <bfs+0x184>
  401678:	f94037a0 	ldr	x0, [x29, #104]
  40167c:	b9400000 	ldr	w0, [x0]
  401680:	51000400 	sub	w0, w0, #0x1
  401684:	93407c00 	sxtw	x0, w0
  401688:	d37ef400 	lsl	x0, x0, #2
  40168c:	9100e3a1 	add	x1, x29, #0x38
  401690:	b8606820 	ldr	w0, [x1, x0]
  401694:	7100001f 	cmp	w0, #0x0
  401698:	540003e1 	b.ne	401714 <bfs+0x184>  // b.any
  40169c:	f94037a0 	ldr	x0, [x29, #104]
  4016a0:	b9400000 	ldr	w0, [x0]
  4016a4:	51000400 	sub	w0, w0, #0x1
  4016a8:	93407c00 	sxtw	x0, w0
  4016ac:	d37cec00 	lsl	x0, x0, #4
  4016b0:	8b000260 	add	x0, x19, x0
  4016b4:	39401000 	ldrb	w0, [x0, #4]
  4016b8:	2a0003e1 	mov	w1, w0
  4016bc:	d0000000 	adrp	x0, 403000 <main+0x790>
  4016c0:	910ba000 	add	x0, x0, #0x2e8
  4016c4:	97fffbfb 	bl	4006b0 <printf@plt>
  4016c8:	f94037a0 	ldr	x0, [x29, #104]
  4016cc:	b9400000 	ldr	w0, [x0]
  4016d0:	51000400 	sub	w0, w0, #0x1
  4016d4:	93407c00 	sxtw	x0, w0
  4016d8:	d37ef400 	lsl	x0, x0, #2
  4016dc:	9100e3a1 	add	x1, x29, #0x38
  4016e0:	52800022 	mov	w2, #0x1                   	// #1
  4016e4:	b8206822 	str	w2, [x1, x0]
  4016e8:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  4016ec:	910bc000 	add	x0, x0, #0x2f0
  4016f0:	f9400002 	ldr	x2, [x0]
  4016f4:	f94037a0 	ldr	x0, [x29, #104]
  4016f8:	b9400000 	ldr	w0, [x0]
  4016fc:	2a0003e1 	mov	w1, w0
  401700:	aa0203e0 	mov	x0, x2
  401704:	97ffff12 	bl	40134c <addqueue>
  401708:	f94037a0 	ldr	x0, [x29, #104]
  40170c:	f9400400 	ldr	x0, [x0, #8]
  401710:	f90037a0 	str	x0, [x29, #104]
  401714:	f94037a0 	ldr	x0, [x29, #104]
  401718:	f100001f 	cmp	x0, #0x0
  40171c:	54fffae1 	b.ne	401678 <bfs+0xe8>  // b.any
  401720:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  401724:	910bc000 	add	x0, x0, #0x2f0
  401728:	f9400000 	ldr	x0, [x0]
  40172c:	97fffef9 	bl	401310 <empty>
  401730:	7100001f 	cmp	w0, #0x0
  401734:	54fff880 	b.eq	401644 <bfs+0xb4>  // b.none
  401738:	d503201f 	nop
  40173c:	f9400bf3 	ldr	x19, [sp, #16]
  401740:	a8c77bfd 	ldp	x29, x30, [sp], #112
  401744:	d65f03c0 	ret

0000000000401748 <initstack>:
  401748:	d10043ff 	sub	sp, sp, #0x10
  40174c:	f90007e0 	str	x0, [sp, #8]
  401750:	f94007e0 	ldr	x0, [sp, #8]
  401754:	b900281f 	str	wzr, [x0, #40]
  401758:	52800020 	mov	w0, #0x1                   	// #1
  40175c:	910043ff 	add	sp, sp, #0x10
  401760:	d65f03c0 	ret

0000000000401764 <push>:
  401764:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  401768:	910003fd 	mov	x29, sp
  40176c:	f9000fa0 	str	x0, [x29, #24]
  401770:	b90017a1 	str	w1, [x29, #20]
  401774:	f9400fa0 	ldr	x0, [x29, #24]
  401778:	b9402800 	ldr	w0, [x0, #40]
  40177c:	7100281f 	cmp	w0, #0xa
  401780:	540000a1 	b.ne	401794 <push+0x30>  // b.any
  401784:	d0000000 	adrp	x0, 403000 <main+0x790>
  401788:	910bc000 	add	x0, x0, #0x2f0
  40178c:	97fffbbd 	bl	400680 <puts@plt>
  401790:	1400000c 	b	4017c0 <push+0x5c>
  401794:	f9400fa0 	ldr	x0, [x29, #24]
  401798:	b9402800 	ldr	w0, [x0, #40]
  40179c:	11000401 	add	w1, w0, #0x1
  4017a0:	f9400fa0 	ldr	x0, [x29, #24]
  4017a4:	b9002801 	str	w1, [x0, #40]
  4017a8:	f9400fa0 	ldr	x0, [x29, #24]
  4017ac:	b9402801 	ldr	w1, [x0, #40]
  4017b0:	f9400fa0 	ldr	x0, [x29, #24]
  4017b4:	93407c21 	sxtw	x1, w1
  4017b8:	b94017a2 	ldr	w2, [x29, #20]
  4017bc:	b8217802 	str	w2, [x0, x1, lsl #2]
  4017c0:	d503201f 	nop
  4017c4:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4017c8:	d65f03c0 	ret

00000000004017cc <pop>:
  4017cc:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4017d0:	910003fd 	mov	x29, sp
  4017d4:	f9000fa0 	str	x0, [x29, #24]
  4017d8:	f9400fa0 	ldr	x0, [x29, #24]
  4017dc:	b9402800 	ldr	w0, [x0, #40]
  4017e0:	7100001f 	cmp	w0, #0x0
  4017e4:	540000a1 	b.ne	4017f8 <pop+0x2c>  // b.any
  4017e8:	d0000000 	adrp	x0, 403000 <main+0x790>
  4017ec:	910c2000 	add	x0, x0, #0x308
  4017f0:	97fffba4 	bl	400680 <puts@plt>
  4017f4:	1400000c 	b	401824 <pop+0x58>
  4017f8:	f9400fa0 	ldr	x0, [x29, #24]
  4017fc:	b9402801 	ldr	w1, [x0, #40]
  401800:	f9400fa0 	ldr	x0, [x29, #24]
  401804:	93407c21 	sxtw	x1, w1
  401808:	b8617800 	ldr	w0, [x0, x1, lsl #2]
  40180c:	b9002fa0 	str	w0, [x29, #44]
  401810:	f9400fa0 	ldr	x0, [x29, #24]
  401814:	b9402800 	ldr	w0, [x0, #40]
  401818:	51000401 	sub	w1, w0, #0x1
  40181c:	f9400fa0 	ldr	x0, [x29, #24]
  401820:	b9002801 	str	w1, [x0, #40]
  401824:	b9402fa0 	ldr	w0, [x29, #44]
  401828:	a8c37bfd 	ldp	x29, x30, [sp], #48
  40182c:	d65f03c0 	ret

0000000000401830 <stackempty>:
  401830:	d10043ff 	sub	sp, sp, #0x10
  401834:	f90007e0 	str	x0, [sp, #8]
  401838:	f94007e0 	ldr	x0, [sp, #8]
  40183c:	b9402800 	ldr	w0, [x0, #40]
  401840:	7100281f 	cmp	w0, #0xa
  401844:	54000061 	b.ne	401850 <stackempty+0x20>  // b.any
  401848:	52800020 	mov	w0, #0x1                   	// #1
  40184c:	14000002 	b	401854 <stackempty+0x24>
  401850:	52800000 	mov	w0, #0x0                   	// #0
  401854:	910043ff 	add	sp, sp, #0x10
  401858:	d65f03c0 	ret

000000000040185c <topsort>:
  40185c:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  401860:	910003fd 	mov	x29, sp
  401864:	f9000bf3 	str	x19, [sp, #16]
  401868:	aa0003f3 	mov	x19, x0
  40186c:	d0000000 	adrp	x0, 403000 <main+0x790>
  401870:	910c8000 	add	x0, x0, #0x320
  401874:	97fffb83 	bl	400680 <puts@plt>
  401878:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  40187c:	910ba000 	add	x0, x0, #0x2e8
  401880:	f9400000 	ldr	x0, [x0]
  401884:	97ffffb1 	bl	401748 <initstack>
  401888:	b9003fbf 	str	wzr, [x29, #60]
  40188c:	14000014 	b	4018dc <topsort+0x80>
  401890:	b9803fa0 	ldrsw	x0, [x29, #60]
  401894:	d37cec00 	lsl	x0, x0, #4
  401898:	8b000260 	add	x0, x19, x0
  40189c:	b9400000 	ldr	w0, [x0]
  4018a0:	7100001f 	cmp	w0, #0x0
  4018a4:	54000161 	b.ne	4018d0 <topsort+0x74>  // b.any
  4018a8:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  4018ac:	910ba000 	add	x0, x0, #0x2e8
  4018b0:	f9400002 	ldr	x2, [x0]
  4018b4:	b9803fa0 	ldrsw	x0, [x29, #60]
  4018b8:	d37cec00 	lsl	x0, x0, #4
  4018bc:	8b000260 	add	x0, x19, x0
  4018c0:	39401000 	ldrb	w0, [x0, #4]
  4018c4:	2a0003e1 	mov	w1, w0
  4018c8:	aa0203e0 	mov	x0, x2
  4018cc:	97ffffa6 	bl	401764 <push>
  4018d0:	b9403fa0 	ldr	w0, [x29, #60]
  4018d4:	11000400 	add	w0, w0, #0x1
  4018d8:	b9003fa0 	str	w0, [x29, #60]
  4018dc:	b940a260 	ldr	w0, [x19, #160]
  4018e0:	b9403fa1 	ldr	w1, [x29, #60]
  4018e4:	6b00003f 	cmp	w1, w0
  4018e8:	54fffd4b 	b.lt	401890 <topsort+0x34>  // b.tstop
  4018ec:	b9003bbf 	str	wzr, [x29, #56]
  4018f0:	14000039 	b	4019d4 <topsort+0x178>
  4018f4:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  4018f8:	910ba000 	add	x0, x0, #0x2e8
  4018fc:	f9400000 	ldr	x0, [x0]
  401900:	97ffffb3 	bl	4017cc <pop>
  401904:	b9003fa0 	str	w0, [x29, #60]
  401908:	b9803fa0 	ldrsw	x0, [x29, #60]
  40190c:	d37cec00 	lsl	x0, x0, #4
  401910:	8b000260 	add	x0, x19, x0
  401914:	39401000 	ldrb	w0, [x0, #4]
  401918:	2a0003e1 	mov	w1, w0
  40191c:	d0000000 	adrp	x0, 403000 <main+0x790>
  401920:	910ce000 	add	x0, x0, #0x338
  401924:	97fffb63 	bl	4006b0 <printf@plt>
  401928:	b9403ba0 	ldr	w0, [x29, #56]
  40192c:	11000400 	add	w0, w0, #0x1
  401930:	b9003ba0 	str	w0, [x29, #56]
  401934:	b9803fa0 	ldrsw	x0, [x29, #60]
  401938:	d37cec00 	lsl	x0, x0, #4
  40193c:	8b000260 	add	x0, x19, x0
  401940:	f9400400 	ldr	x0, [x0, #8]
  401944:	f9001ba0 	str	x0, [x29, #48]
  401948:	14000020 	b	4019c8 <topsort+0x16c>
  40194c:	f9401ba0 	ldr	x0, [x29, #48]
  401950:	b9400000 	ldr	w0, [x0]
  401954:	b9002fa0 	str	w0, [x29, #44]
  401958:	b9402fa0 	ldr	w0, [x29, #44]
  40195c:	51000400 	sub	w0, w0, #0x1
  401960:	93407c01 	sxtw	x1, w0
  401964:	d37cec21 	lsl	x1, x1, #4
  401968:	8b010261 	add	x1, x19, x1
  40196c:	b9400021 	ldr	w1, [x1]
  401970:	51000422 	sub	w2, w1, #0x1
  401974:	93407c01 	sxtw	x1, w0
  401978:	d37cec21 	lsl	x1, x1, #4
  40197c:	8b010261 	add	x1, x19, x1
  401980:	b9000022 	str	w2, [x1]
  401984:	93407c00 	sxtw	x0, w0
  401988:	d37cec00 	lsl	x0, x0, #4
  40198c:	8b000260 	add	x0, x19, x0
  401990:	b9400000 	ldr	w0, [x0]
  401994:	7100001f 	cmp	w0, #0x0
  401998:	54000121 	b.ne	4019bc <topsort+0x160>  // b.any
  40199c:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  4019a0:	910ba000 	add	x0, x0, #0x2e8
  4019a4:	f9400002 	ldr	x2, [x0]
  4019a8:	b9402fa0 	ldr	w0, [x29, #44]
  4019ac:	51000400 	sub	w0, w0, #0x1
  4019b0:	2a0003e1 	mov	w1, w0
  4019b4:	aa0203e0 	mov	x0, x2
  4019b8:	97ffff6b 	bl	401764 <push>
  4019bc:	f9401ba0 	ldr	x0, [x29, #48]
  4019c0:	f9400400 	ldr	x0, [x0, #8]
  4019c4:	f9001ba0 	str	x0, [x29, #48]
  4019c8:	f9401ba0 	ldr	x0, [x29, #48]
  4019cc:	f100001f 	cmp	x0, #0x0
  4019d0:	54fffbe1 	b.ne	40194c <topsort+0xf0>  // b.any
  4019d4:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  4019d8:	910ba000 	add	x0, x0, #0x2e8
  4019dc:	f9400000 	ldr	x0, [x0]
  4019e0:	97ffff94 	bl	401830 <stackempty>
  4019e4:	7100001f 	cmp	w0, #0x0
  4019e8:	54fff860 	b.eq	4018f4 <topsort+0x98>  // b.none
  4019ec:	b940a260 	ldr	w0, [x19, #160]
  4019f0:	b9403ba1 	ldr	w1, [x29, #56]
  4019f4:	6b00003f 	cmp	w1, w0
  4019f8:	540000ca 	b.ge	401a10 <topsort+0x1b4>  // b.tcont
  4019fc:	d0000000 	adrp	x0, 403000 <main+0x790>
  401a00:	910d0000 	add	x0, x0, #0x340
  401a04:	97fffb1f 	bl	400680 <puts@plt>
  401a08:	52800000 	mov	w0, #0x0                   	// #0
  401a0c:	14000002 	b	401a14 <topsort+0x1b8>
  401a10:	52800020 	mov	w0, #0x1                   	// #1
  401a14:	f9400bf3 	ldr	x19, [sp, #16]
  401a18:	a8c47bfd 	ldp	x29, x30, [sp], #64
  401a1c:	d65f03c0 	ret

0000000000401a20 <prim>:
  401a20:	a9b87bfd 	stp	x29, x30, [sp, #-128]!
  401a24:	910003fd 	mov	x29, sp
  401a28:	f9000bf3 	str	x19, [sp, #16]
  401a2c:	aa0003f3 	mov	x19, x0
  401a30:	d0000000 	adrp	x0, 403000 <main+0x790>
  401a34:	910d6000 	add	x0, x0, #0x358
  401a38:	97fffb12 	bl	400680 <puts@plt>
  401a3c:	52800020 	mov	w0, #0x1                   	// #1
  401a40:	b9007fa0 	str	w0, [x29, #124]
  401a44:	14000010 	b	401a84 <prim+0x64>
  401a48:	b9807fa0 	ldrsw	x0, [x29, #124]
  401a4c:	91009000 	add	x0, x0, #0x24
  401a50:	b8607a62 	ldr	w2, [x19, x0, lsl #2]
  401a54:	b9807fa0 	ldrsw	x0, [x29, #124]
  401a58:	d37ef400 	lsl	x0, x0, #2
  401a5c:	910123a1 	add	x1, x29, #0x48
  401a60:	b8206822 	str	w2, [x1, x0]
  401a64:	b9807fa0 	ldrsw	x0, [x29, #124]
  401a68:	d37ef400 	lsl	x0, x0, #2
  401a6c:	910083a1 	add	x1, x29, #0x20
  401a70:	52800022 	mov	w2, #0x1                   	// #1
  401a74:	b8206822 	str	w2, [x1, x0]
  401a78:	b9407fa0 	ldr	w0, [x29, #124]
  401a7c:	11000400 	add	w0, w0, #0x1
  401a80:	b9007fa0 	str	w0, [x29, #124]
  401a84:	b9408660 	ldr	w0, [x19, #132]
  401a88:	b9407fa1 	ldr	w1, [x29, #124]
  401a8c:	6b00003f 	cmp	w1, w0
  401a90:	54fffdcb 	b.lt	401a48 <prim+0x28>  // b.tstop
  401a94:	b90027bf 	str	wzr, [x29, #36]
  401a98:	52800020 	mov	w0, #0x1                   	// #1
  401a9c:	b9007ba0 	str	w0, [x29, #120]
  401aa0:	52800020 	mov	w0, #0x1                   	// #1
  401aa4:	b9007fa0 	str	w0, [x29, #124]
  401aa8:	14000073 	b	401c74 <prim+0x254>
  401aac:	b9807ba0 	ldrsw	x0, [x29, #120]
  401ab0:	d37ef400 	lsl	x0, x0, #2
  401ab4:	910123a1 	add	x1, x29, #0x48
  401ab8:	b8606820 	ldr	w0, [x1, x0]
  401abc:	b90073a0 	str	w0, [x29, #112]
  401ac0:	b9407fa0 	ldr	w0, [x29, #124]
  401ac4:	b90077a0 	str	w0, [x29, #116]
  401ac8:	52800020 	mov	w0, #0x1                   	// #1
  401acc:	b9007ba0 	str	w0, [x29, #120]
  401ad0:	14000018 	b	401b30 <prim+0x110>
  401ad4:	b9807ba0 	ldrsw	x0, [x29, #120]
  401ad8:	d37ef400 	lsl	x0, x0, #2
  401adc:	910123a1 	add	x1, x29, #0x48
  401ae0:	b8606820 	ldr	w0, [x1, x0]
  401ae4:	b94073a1 	ldr	w1, [x29, #112]
  401ae8:	6b00003f 	cmp	w1, w0
  401aec:	540001cd 	b.le	401b24 <prim+0x104>
  401af0:	b9807ba0 	ldrsw	x0, [x29, #120]
  401af4:	d37ef400 	lsl	x0, x0, #2
  401af8:	910083a1 	add	x1, x29, #0x20
  401afc:	b8606820 	ldr	w0, [x1, x0]
  401b00:	7100001f 	cmp	w0, #0x0
  401b04:	54000100 	b.eq	401b24 <prim+0x104>  // b.none
  401b08:	b9807ba0 	ldrsw	x0, [x29, #120]
  401b0c:	d37ef400 	lsl	x0, x0, #2
  401b10:	910123a1 	add	x1, x29, #0x48
  401b14:	b8606820 	ldr	w0, [x1, x0]
  401b18:	b90073a0 	str	w0, [x29, #112]
  401b1c:	b9407ba0 	ldr	w0, [x29, #120]
  401b20:	b90077a0 	str	w0, [x29, #116]
  401b24:	b9407ba0 	ldr	w0, [x29, #120]
  401b28:	11000400 	add	w0, w0, #0x1
  401b2c:	b9007ba0 	str	w0, [x29, #120]
  401b30:	b9408660 	ldr	w0, [x19, #132]
  401b34:	b9407ba1 	ldr	w1, [x29, #120]
  401b38:	6b00003f 	cmp	w1, w0
  401b3c:	54fffccb 	b.lt	401ad4 <prim+0xb4>  // b.tstop
  401b40:	b94077a0 	ldr	w0, [x29, #116]
  401b44:	51000400 	sub	w0, w0, #0x1
  401b48:	93407c00 	sxtw	x0, w0
  401b4c:	8b000260 	add	x0, x19, x0
  401b50:	3941e000 	ldrb	w0, [x0, #120]
  401b54:	2a0003e3 	mov	w3, w0
  401b58:	b94077a0 	ldr	w0, [x29, #116]
  401b5c:	51000400 	sub	w0, w0, #0x1
  401b60:	93407c00 	sxtw	x0, w0
  401b64:	d37ef400 	lsl	x0, x0, #2
  401b68:	910083a1 	add	x1, x29, #0x20
  401b6c:	b8606820 	ldr	w0, [x1, x0]
  401b70:	93407c00 	sxtw	x0, w0
  401b74:	8b000260 	add	x0, x19, x0
  401b78:	3941e000 	ldrb	w0, [x0, #120]
  401b7c:	2a0003e1 	mov	w1, w0
  401b80:	d0000000 	adrp	x0, 403000 <main+0x790>
  401b84:	910e0000 	add	x0, x0, #0x380
  401b88:	2a0103e2 	mov	w2, w1
  401b8c:	2a0303e1 	mov	w1, w3
  401b90:	97fffac8 	bl	4006b0 <printf@plt>
  401b94:	b98077a0 	ldrsw	x0, [x29, #116]
  401b98:	d37ef400 	lsl	x0, x0, #2
  401b9c:	910083a1 	add	x1, x29, #0x20
  401ba0:	b820683f 	str	wzr, [x1, x0]
  401ba4:	52800020 	mov	w0, #0x1                   	// #1
  401ba8:	b9007ba0 	str	w0, [x29, #120]
  401bac:	1400002b 	b	401c58 <prim+0x238>
  401bb0:	b9807ba2 	ldrsw	x2, [x29, #120]
  401bb4:	b98077a1 	ldrsw	x1, [x29, #116]
  401bb8:	aa0103e0 	mov	x0, x1
  401bbc:	d37ef400 	lsl	x0, x0, #2
  401bc0:	8b010000 	add	x0, x0, x1
  401bc4:	d37ff800 	lsl	x0, x0, #1
  401bc8:	8b020000 	add	x0, x0, x2
  401bcc:	91009000 	add	x0, x0, #0x24
  401bd0:	b8607a61 	ldr	w1, [x19, x0, lsl #2]
  401bd4:	b9807ba0 	ldrsw	x0, [x29, #120]
  401bd8:	d37ef400 	lsl	x0, x0, #2
  401bdc:	910123a2 	add	x2, x29, #0x48
  401be0:	b8606840 	ldr	w0, [x2, x0]
  401be4:	6b00003f 	cmp	w1, w0
  401be8:	5400032a 	b.ge	401c4c <prim+0x22c>  // b.tcont
  401bec:	b9807ba0 	ldrsw	x0, [x29, #120]
  401bf0:	d37ef400 	lsl	x0, x0, #2
  401bf4:	910083a1 	add	x1, x29, #0x20
  401bf8:	b8606820 	ldr	w0, [x1, x0]
  401bfc:	7100001f 	cmp	w0, #0x0
  401c00:	54000260 	b.eq	401c4c <prim+0x22c>  // b.none
  401c04:	b9807ba2 	ldrsw	x2, [x29, #120]
  401c08:	b98077a1 	ldrsw	x1, [x29, #116]
  401c0c:	aa0103e0 	mov	x0, x1
  401c10:	d37ef400 	lsl	x0, x0, #2
  401c14:	8b010000 	add	x0, x0, x1
  401c18:	d37ff800 	lsl	x0, x0, #1
  401c1c:	8b020000 	add	x0, x0, x2
  401c20:	91009000 	add	x0, x0, #0x24
  401c24:	b8607a62 	ldr	w2, [x19, x0, lsl #2]
  401c28:	b9807ba0 	ldrsw	x0, [x29, #120]
  401c2c:	d37ef400 	lsl	x0, x0, #2
  401c30:	910123a1 	add	x1, x29, #0x48
  401c34:	b8206822 	str	w2, [x1, x0]
  401c38:	b9807ba0 	ldrsw	x0, [x29, #120]
  401c3c:	d37ef400 	lsl	x0, x0, #2
  401c40:	910083a1 	add	x1, x29, #0x20
  401c44:	b94077a2 	ldr	w2, [x29, #116]
  401c48:	b8206822 	str	w2, [x1, x0]
  401c4c:	b9407ba0 	ldr	w0, [x29, #120]
  401c50:	11000400 	add	w0, w0, #0x1
  401c54:	b9007ba0 	str	w0, [x29, #120]
  401c58:	b9408660 	ldr	w0, [x19, #132]
  401c5c:	b9407ba1 	ldr	w1, [x29, #120]
  401c60:	6b00003f 	cmp	w1, w0
  401c64:	54fffa6b 	b.lt	401bb0 <prim+0x190>  // b.tstop
  401c68:	b9407fa0 	ldr	w0, [x29, #124]
  401c6c:	11000400 	add	w0, w0, #0x1
  401c70:	b9007fa0 	str	w0, [x29, #124]
  401c74:	b9408660 	ldr	w0, [x19, #132]
  401c78:	b9407fa1 	ldr	w1, [x29, #124]
  401c7c:	6b00003f 	cmp	w1, w0
  401c80:	54fff16b 	b.lt	401aac <prim+0x8c>  // b.tstop
  401c84:	d503201f 	nop
  401c88:	f9400bf3 	ldr	x19, [sp, #16]
  401c8c:	a8c87bfd 	ldp	x29, x30, [sp], #128
  401c90:	d65f03c0 	ret

0000000000401c94 <toporder>:
  401c94:	a9bb7bfd 	stp	x29, x30, [sp, #-80]!
  401c98:	910003fd 	mov	x29, sp
  401c9c:	f9000bf3 	str	x19, [sp, #16]
  401ca0:	aa0003f3 	mov	x19, x0
  401ca4:	f90017a1 	str	x1, [x29, #40]
  401ca8:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  401cac:	910ba000 	add	x0, x0, #0x2e8
  401cb0:	f9400000 	ldr	x0, [x0]
  401cb4:	97fffea5 	bl	401748 <initstack>
  401cb8:	f94017a0 	ldr	x0, [x29, #40]
  401cbc:	97fffea3 	bl	401748 <initstack>
  401cc0:	b9004fbf 	str	wzr, [x29, #76]
  401cc4:	1400000f 	b	401d00 <toporder+0x6c>
  401cc8:	b9804fa0 	ldrsw	x0, [x29, #76]
  401ccc:	d37cec00 	lsl	x0, x0, #4
  401cd0:	8b000260 	add	x0, x19, x0
  401cd4:	b9400000 	ldr	w0, [x0]
  401cd8:	7100001f 	cmp	w0, #0x0
  401cdc:	540000c1 	b.ne	401cf4 <toporder+0x60>  // b.any
  401ce0:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  401ce4:	910ba000 	add	x0, x0, #0x2e8
  401ce8:	f9400000 	ldr	x0, [x0]
  401cec:	b9404fa1 	ldr	w1, [x29, #76]
  401cf0:	97fffe9d 	bl	401764 <push>
  401cf4:	b9404fa0 	ldr	w0, [x29, #76]
  401cf8:	11000400 	add	w0, w0, #0x1
  401cfc:	b9004fa0 	str	w0, [x29, #76]
  401d00:	b940a260 	ldr	w0, [x19, #160]
  401d04:	b9404fa1 	ldr	w1, [x29, #76]
  401d08:	6b00003f 	cmp	w1, w0
  401d0c:	54fffdeb 	b.lt	401cc8 <toporder+0x34>  // b.tstop
  401d10:	b9004bbf 	str	wzr, [x29, #72]
  401d14:	b9004fbf 	str	wzr, [x29, #76]
  401d18:	14000008 	b	401d38 <toporder+0xa4>
  401d1c:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  401d20:	91028000 	add	x0, x0, #0xa0
  401d24:	b9804fa1 	ldrsw	x1, [x29, #76]
  401d28:	b821781f 	str	wzr, [x0, x1, lsl #2]
  401d2c:	b9404fa0 	ldr	w0, [x29, #76]
  401d30:	11000400 	add	w0, w0, #0x1
  401d34:	b9004fa0 	str	w0, [x29, #76]
  401d38:	b940a260 	ldr	w0, [x19, #160]
  401d3c:	b9404fa1 	ldr	w1, [x29, #76]
  401d40:	6b00003f 	cmp	w1, w0
  401d44:	54fffecb 	b.lt	401d1c <toporder+0x88>  // b.tstop
  401d48:	14000050 	b	401e88 <toporder+0x1f4>
  401d4c:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  401d50:	910ba000 	add	x0, x0, #0x2e8
  401d54:	f9400000 	ldr	x0, [x0]
  401d58:	97fffe9d 	bl	4017cc <pop>
  401d5c:	b9003fa0 	str	w0, [x29, #60]
  401d60:	b9403fa1 	ldr	w1, [x29, #60]
  401d64:	f94017a0 	ldr	x0, [x29, #40]
  401d68:	97fffe7f 	bl	401764 <push>
  401d6c:	b9404ba0 	ldr	w0, [x29, #72]
  401d70:	11000400 	add	w0, w0, #0x1
  401d74:	b9004ba0 	str	w0, [x29, #72]
  401d78:	b9803fa0 	ldrsw	x0, [x29, #60]
  401d7c:	d37cec00 	lsl	x0, x0, #4
  401d80:	8b000260 	add	x0, x19, x0
  401d84:	f9400400 	ldr	x0, [x0, #8]
  401d88:	f90023a0 	str	x0, [x29, #64]
  401d8c:	1400003c 	b	401e7c <toporder+0x1e8>
  401d90:	f94023a0 	ldr	x0, [x29, #64]
  401d94:	b9400000 	ldr	w0, [x0]
  401d98:	b9003ba0 	str	w0, [x29, #56]
  401d9c:	b9403ba0 	ldr	w0, [x29, #56]
  401da0:	51000400 	sub	w0, w0, #0x1
  401da4:	93407c01 	sxtw	x1, w0
  401da8:	d37cec21 	lsl	x1, x1, #4
  401dac:	8b010261 	add	x1, x19, x1
  401db0:	b9400021 	ldr	w1, [x1]
  401db4:	51000422 	sub	w2, w1, #0x1
  401db8:	93407c01 	sxtw	x1, w0
  401dbc:	d37cec21 	lsl	x1, x1, #4
  401dc0:	8b010261 	add	x1, x19, x1
  401dc4:	b9000022 	str	w2, [x1]
  401dc8:	93407c00 	sxtw	x0, w0
  401dcc:	d37cec00 	lsl	x0, x0, #4
  401dd0:	8b000260 	add	x0, x19, x0
  401dd4:	b9400000 	ldr	w0, [x0]
  401dd8:	7100001f 	cmp	w0, #0x0
  401ddc:	54000121 	b.ne	401e00 <toporder+0x16c>  // b.any
  401de0:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  401de4:	910ba000 	add	x0, x0, #0x2e8
  401de8:	f9400002 	ldr	x2, [x0]
  401dec:	b9403ba0 	ldr	w0, [x29, #56]
  401df0:	51000400 	sub	w0, w0, #0x1
  401df4:	2a0003e1 	mov	w1, w0
  401df8:	aa0203e0 	mov	x0, x2
  401dfc:	97fffe5a 	bl	401764 <push>
  401e00:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  401e04:	91028000 	add	x0, x0, #0xa0
  401e08:	b9803fa1 	ldrsw	x1, [x29, #60]
  401e0c:	b8617801 	ldr	w1, [x0, x1, lsl #2]
  401e10:	f94023a0 	ldr	x0, [x29, #64]
  401e14:	b9400400 	ldr	w0, [x0, #4]
  401e18:	0b000021 	add	w1, w1, w0
  401e1c:	b9403ba0 	ldr	w0, [x29, #56]
  401e20:	51000402 	sub	w2, w0, #0x1
  401e24:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  401e28:	91028000 	add	x0, x0, #0xa0
  401e2c:	93407c42 	sxtw	x2, w2
  401e30:	b8627800 	ldr	w0, [x0, x2, lsl #2]
  401e34:	6b00003f 	cmp	w1, w0
  401e38:	540001cd 	b.le	401e70 <toporder+0x1dc>
  401e3c:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  401e40:	91028000 	add	x0, x0, #0xa0
  401e44:	b9803fa1 	ldrsw	x1, [x29, #60]
  401e48:	b8617801 	ldr	w1, [x0, x1, lsl #2]
  401e4c:	f94023a0 	ldr	x0, [x29, #64]
  401e50:	b9400400 	ldr	w0, [x0, #4]
  401e54:	b9403ba2 	ldr	w2, [x29, #56]
  401e58:	51000443 	sub	w3, w2, #0x1
  401e5c:	0b000022 	add	w2, w1, w0
  401e60:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  401e64:	91028000 	add	x0, x0, #0xa0
  401e68:	93407c61 	sxtw	x1, w3
  401e6c:	b8217802 	str	w2, [x0, x1, lsl #2]
  401e70:	f94023a0 	ldr	x0, [x29, #64]
  401e74:	f9400400 	ldr	x0, [x0, #8]
  401e78:	f90023a0 	str	x0, [x29, #64]
  401e7c:	f94023a0 	ldr	x0, [x29, #64]
  401e80:	f100001f 	cmp	x0, #0x0
  401e84:	54fff861 	b.ne	401d90 <toporder+0xfc>  // b.any
  401e88:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  401e8c:	910ba000 	add	x0, x0, #0x2e8
  401e90:	f9400000 	ldr	x0, [x0]
  401e94:	97fffe67 	bl	401830 <stackempty>
  401e98:	7100001f 	cmp	w0, #0x0
  401e9c:	54fff580 	b.eq	401d4c <toporder+0xb8>  // b.none
  401ea0:	b940a260 	ldr	w0, [x19, #160]
  401ea4:	b9404ba1 	ldr	w1, [x29, #72]
  401ea8:	6b00003f 	cmp	w1, w0
  401eac:	5400006a 	b.ge	401eb8 <toporder+0x224>  // b.tcont
  401eb0:	52800000 	mov	w0, #0x0                   	// #0
  401eb4:	14000002 	b	401ebc <toporder+0x228>
  401eb8:	52800020 	mov	w0, #0x1                   	// #1
  401ebc:	f9400bf3 	ldr	x19, [sp, #16]
  401ec0:	a8c57bfd 	ldp	x29, x30, [sp], #80
  401ec4:	d65f03c0 	ret

0000000000401ec8 <criticalpath>:
  401ec8:	a9b17bfd 	stp	x29, x30, [sp, #-240]!
  401ecc:	910003fd 	mov	x29, sp
  401ed0:	a90153f3 	stp	x19, x20, [sp, #16]
  401ed4:	aa0003f3 	mov	x19, x0
  401ed8:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  401edc:	91026000 	add	x0, x0, #0x98
  401ee0:	f9400014 	ldr	x20, [x0]
  401ee4:	910083a0 	add	x0, x29, #0x20
  401ee8:	aa1303e3 	mov	x3, x19
  401eec:	d2801601 	mov	x1, #0xb0                  	// #176
  401ef0:	aa0103e2 	mov	x2, x1
  401ef4:	aa0303e1 	mov	x1, x3
  401ef8:	97fff9ce 	bl	400630 <memcpy@plt>
  401efc:	910083a0 	add	x0, x29, #0x20
  401f00:	aa1403e1 	mov	x1, x20
  401f04:	97ffff64 	bl	401c94 <toporder>
  401f08:	7100001f 	cmp	w0, #0x0
  401f0c:	54000061 	b.ne	401f18 <criticalpath+0x50>  // b.any
  401f10:	52800000 	mov	w0, #0x0                   	// #0
  401f14:	14000087 	b	402130 <criticalpath+0x268>
  401f18:	b900efbf 	str	wzr, [x29, #236]
  401f1c:	1400000e 	b	401f54 <criticalpath+0x8c>
  401f20:	b940efa0 	ldr	w0, [x29, #236]
  401f24:	51000401 	sub	w1, w0, #0x1
  401f28:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  401f2c:	91028000 	add	x0, x0, #0xa0
  401f30:	93407c21 	sxtw	x1, w1
  401f34:	b8617802 	ldr	w2, [x0, x1, lsl #2]
  401f38:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  401f3c:	9101c000 	add	x0, x0, #0x70
  401f40:	b980efa1 	ldrsw	x1, [x29, #236]
  401f44:	b8217802 	str	w2, [x0, x1, lsl #2]
  401f48:	b940efa0 	ldr	w0, [x29, #236]
  401f4c:	11000400 	add	w0, w0, #0x1
  401f50:	b900efa0 	str	w0, [x29, #236]
  401f54:	b940a260 	ldr	w0, [x19, #160]
  401f58:	b940efa1 	ldr	w1, [x29, #236]
  401f5c:	6b00003f 	cmp	w1, w0
  401f60:	54fffe0b 	b.lt	401f20 <criticalpath+0x58>  // b.tstop
  401f64:	d0000000 	adrp	x0, 403000 <main+0x790>
  401f68:	910e4000 	add	x0, x0, #0x390
  401f6c:	97fff9c5 	bl	400680 <puts@plt>
  401f70:	1400002e 	b	402028 <criticalpath+0x160>
  401f74:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  401f78:	91026000 	add	x0, x0, #0x98
  401f7c:	f9400000 	ldr	x0, [x0]
  401f80:	97fffe13 	bl	4017cc <pop>
  401f84:	b900eba0 	str	w0, [x29, #232]
  401f88:	b980eba0 	ldrsw	x0, [x29, #232]
  401f8c:	d37cec00 	lsl	x0, x0, #4
  401f90:	8b000260 	add	x0, x19, x0
  401f94:	f9400400 	ldr	x0, [x0, #8]
  401f98:	f90073a0 	str	x0, [x29, #224]
  401f9c:	14000020 	b	40201c <criticalpath+0x154>
  401fa0:	f94073a0 	ldr	x0, [x29, #224]
  401fa4:	b9400000 	ldr	w0, [x0]
  401fa8:	b900dfa0 	str	w0, [x29, #220]
  401fac:	f94073a0 	ldr	x0, [x29, #224]
  401fb0:	b9400400 	ldr	w0, [x0, #4]
  401fb4:	b900dba0 	str	w0, [x29, #216]
  401fb8:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  401fbc:	9101c000 	add	x0, x0, #0x70
  401fc0:	b980dfa1 	ldrsw	x1, [x29, #220]
  401fc4:	b8617801 	ldr	w1, [x0, x1, lsl #2]
  401fc8:	b940dba0 	ldr	w0, [x29, #216]
  401fcc:	4b000021 	sub	w1, w1, w0
  401fd0:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  401fd4:	9101c000 	add	x0, x0, #0x70
  401fd8:	b980eba2 	ldrsw	x2, [x29, #232]
  401fdc:	b8627800 	ldr	w0, [x0, x2, lsl #2]
  401fe0:	6b00003f 	cmp	w1, w0
  401fe4:	5400016a 	b.ge	402010 <criticalpath+0x148>  // b.tcont
  401fe8:	f0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  401fec:	9101c000 	add	x0, x0, #0x70
  401ff0:	b980dfa1 	ldrsw	x1, [x29, #220]
  401ff4:	b8617801 	ldr	w1, [x0, x1, lsl #2]
  401ff8:	b940dba0 	ldr	w0, [x29, #216]
  401ffc:	4b000022 	sub	w2, w1, w0
  402000:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402004:	9101c000 	add	x0, x0, #0x70
  402008:	b980eba1 	ldrsw	x1, [x29, #232]
  40200c:	b8217802 	str	w2, [x0, x1, lsl #2]
  402010:	f94073a0 	ldr	x0, [x29, #224]
  402014:	f9400400 	ldr	x0, [x0, #8]
  402018:	f90073a0 	str	x0, [x29, #224]
  40201c:	f94073a0 	ldr	x0, [x29, #224]
  402020:	f100001f 	cmp	x0, #0x0
  402024:	54fffbe1 	b.ne	401fa0 <criticalpath+0xd8>  // b.any
  402028:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  40202c:	91026000 	add	x0, x0, #0x98
  402030:	f9400000 	ldr	x0, [x0]
  402034:	97fffdff 	bl	401830 <stackempty>
  402038:	7100001f 	cmp	w0, #0x0
  40203c:	54fff9c0 	b.eq	401f74 <criticalpath+0xac>  // b.none
  402040:	b900ebbf 	str	wzr, [x29, #232]
  402044:	14000037 	b	402120 <criticalpath+0x258>
  402048:	b980eba0 	ldrsw	x0, [x29, #232]
  40204c:	d37cec00 	lsl	x0, x0, #4
  402050:	8b000260 	add	x0, x19, x0
  402054:	f9400400 	ldr	x0, [x0, #8]
  402058:	f90073a0 	str	x0, [x29, #224]
  40205c:	1400002b 	b	402108 <criticalpath+0x240>
  402060:	f94073a0 	ldr	x0, [x29, #224]
  402064:	b9400000 	ldr	w0, [x0]
  402068:	b900dfa0 	str	w0, [x29, #220]
  40206c:	f94073a0 	ldr	x0, [x29, #224]
  402070:	b9400400 	ldr	w0, [x0, #4]
  402074:	b900dba0 	str	w0, [x29, #216]
  402078:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  40207c:	91028000 	add	x0, x0, #0xa0
  402080:	b980eba1 	ldrsw	x1, [x29, #232]
  402084:	b8617800 	ldr	w0, [x0, x1, lsl #2]
  402088:	b900d7a0 	str	w0, [x29, #212]
  40208c:	b940dfa0 	ldr	w0, [x29, #220]
  402090:	51000401 	sub	w1, w0, #0x1
  402094:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402098:	9101c000 	add	x0, x0, #0x70
  40209c:	93407c21 	sxtw	x1, w1
  4020a0:	b8617801 	ldr	w1, [x0, x1, lsl #2]
  4020a4:	b940dba0 	ldr	w0, [x29, #216]
  4020a8:	4b000020 	sub	w0, w1, w0
  4020ac:	b900d3a0 	str	w0, [x29, #208]
  4020b0:	b940d7a1 	ldr	w1, [x29, #212]
  4020b4:	b940d3a0 	ldr	w0, [x29, #208]
  4020b8:	6b00003f 	cmp	w1, w0
  4020bc:	54000201 	b.ne	4020fc <criticalpath+0x234>  // b.any
  4020c0:	b980eba0 	ldrsw	x0, [x29, #232]
  4020c4:	d37cec00 	lsl	x0, x0, #4
  4020c8:	8b000260 	add	x0, x19, x0
  4020cc:	39401000 	ldrb	w0, [x0, #4]
  4020d0:	2a0003e1 	mov	w1, w0
  4020d4:	b940dfa0 	ldr	w0, [x29, #220]
  4020d8:	51000400 	sub	w0, w0, #0x1
  4020dc:	93407c00 	sxtw	x0, w0
  4020e0:	d37cec00 	lsl	x0, x0, #4
  4020e4:	8b000260 	add	x0, x19, x0
  4020e8:	39401000 	ldrb	w0, [x0, #4]
  4020ec:	2a0003e2 	mov	w2, w0
  4020f0:	b0000000 	adrp	x0, 403000 <main+0x790>
  4020f4:	910ea000 	add	x0, x0, #0x3a8
  4020f8:	97fff96e 	bl	4006b0 <printf@plt>
  4020fc:	f94073a0 	ldr	x0, [x29, #224]
  402100:	f9400400 	ldr	x0, [x0, #8]
  402104:	f90073a0 	str	x0, [x29, #224]
  402108:	f94073a0 	ldr	x0, [x29, #224]
  40210c:	f100001f 	cmp	x0, #0x0
  402110:	54fffa81 	b.ne	402060 <criticalpath+0x198>  // b.any
  402114:	b940eba0 	ldr	w0, [x29, #232]
  402118:	11000400 	add	w0, w0, #0x1
  40211c:	b900eba0 	str	w0, [x29, #232]
  402120:	b940a260 	ldr	w0, [x19, #160]
  402124:	b940eba1 	ldr	w1, [x29, #232]
  402128:	6b00003f 	cmp	w1, w0
  40212c:	54fff8eb 	b.lt	402048 <criticalpath+0x180>  // b.tstop
  402130:	a94153f3 	ldp	x19, x20, [sp, #16]
  402134:	a8cf7bfd 	ldp	x29, x30, [sp], #240
  402138:	d65f03c0 	ret

000000000040213c <shortpath_dijkstra>:
  40213c:	d10903ff 	sub	sp, sp, #0x240
  402140:	a9007bfd 	stp	x29, x30, [sp]
  402144:	910003fd 	mov	x29, sp
  402148:	f9000bf3 	str	x19, [sp, #16]
  40214c:	aa0003f3 	mov	x19, x0
  402150:	b0000000 	adrp	x0, 403000 <main+0x790>
  402154:	910ee000 	add	x0, x0, #0x3b8
  402158:	97fff956 	bl	4006b0 <printf@plt>
  40215c:	910093a1 	add	x1, x29, #0x24
  402160:	b0000000 	adrp	x0, 403000 <main+0x790>
  402164:	910f8000 	add	x0, x0, #0x3e0
  402168:	97fff94e 	bl	4006a0 <__isoc99_scanf@plt>
  40216c:	b94027a0 	ldr	w0, [x29, #36]
  402170:	51000400 	sub	w0, w0, #0x1
  402174:	b90027a0 	str	w0, [x29, #36]
  402178:	b9023fbf 	str	wzr, [x29, #572]
  40217c:	14000020 	b	4021fc <shortpath_dijkstra+0xc0>
  402180:	b9023bbf 	str	wzr, [x29, #568]
  402184:	14000017 	b	4021e0 <shortpath_dijkstra+0xa4>
  402188:	b9823ba2 	ldrsw	x2, [x29, #568]
  40218c:	b9823fa1 	ldrsw	x1, [x29, #572]
  402190:	aa0103e0 	mov	x0, x1
  402194:	d37ef400 	lsl	x0, x0, #2
  402198:	8b010000 	add	x0, x0, x1
  40219c:	d37ff800 	lsl	x0, x0, #1
  4021a0:	8b020000 	add	x0, x0, x2
  4021a4:	91009000 	add	x0, x0, #0x24
  4021a8:	b8607a62 	ldr	w2, [x19, x0, lsl #2]
  4021ac:	b9823ba3 	ldrsw	x3, [x29, #568]
  4021b0:	b9823fa1 	ldrsw	x1, [x29, #572]
  4021b4:	aa0103e0 	mov	x0, x1
  4021b8:	d37ef400 	lsl	x0, x0, #2
  4021bc:	8b010000 	add	x0, x0, x1
  4021c0:	d37ff800 	lsl	x0, x0, #1
  4021c4:	8b030000 	add	x0, x0, x3
  4021c8:	d37ef400 	lsl	x0, x0, #2
  4021cc:	910283a1 	add	x1, x29, #0xa0
  4021d0:	b8206822 	str	w2, [x1, x0]
  4021d4:	b9423ba0 	ldr	w0, [x29, #568]
  4021d8:	11000400 	add	w0, w0, #0x1
  4021dc:	b9023ba0 	str	w0, [x29, #568]
  4021e0:	b9408660 	ldr	w0, [x19, #132]
  4021e4:	b9423ba1 	ldr	w1, [x29, #568]
  4021e8:	6b00003f 	cmp	w1, w0
  4021ec:	54fffceb 	b.lt	402188 <shortpath_dijkstra+0x4c>  // b.tstop
  4021f0:	b9423fa0 	ldr	w0, [x29, #572]
  4021f4:	11000400 	add	w0, w0, #0x1
  4021f8:	b9023fa0 	str	w0, [x29, #572]
  4021fc:	b9408660 	ldr	w0, [x19, #132]
  402200:	b9423fa1 	ldr	w1, [x29, #572]
  402204:	6b00003f 	cmp	w1, w0
  402208:	54fffbcb 	b.lt	402180 <shortpath_dijkstra+0x44>  // b.tstop
  40220c:	b9023fbf 	str	wzr, [x29, #572]
  402210:	14000028 	b	4022b0 <shortpath_dijkstra+0x174>
  402214:	b94027a0 	ldr	w0, [x29, #36]
  402218:	b9823fa2 	ldrsw	x2, [x29, #572]
  40221c:	93407c01 	sxtw	x1, w0
  402220:	aa0103e0 	mov	x0, x1
  402224:	d37ef400 	lsl	x0, x0, #2
  402228:	8b010000 	add	x0, x0, x1
  40222c:	d37ff800 	lsl	x0, x0, #1
  402230:	8b020000 	add	x0, x0, x2
  402234:	d37ef400 	lsl	x0, x0, #2
  402238:	910283a1 	add	x1, x29, #0xa0
  40223c:	b8606822 	ldr	w2, [x1, x0]
  402240:	b9823fa0 	ldrsw	x0, [x29, #572]
  402244:	d37ef400 	lsl	x0, x0, #2
  402248:	9101e3a1 	add	x1, x29, #0x78
  40224c:	b8206822 	str	w2, [x1, x0]
  402250:	b9823fa0 	ldrsw	x0, [x29, #572]
  402254:	d37ef400 	lsl	x0, x0, #2
  402258:	9101e3a1 	add	x1, x29, #0x78
  40225c:	b8606820 	ldr	w0, [x1, x0]
  402260:	710f981f 	cmp	w0, #0x3e6
  402264:	5400018c 	b.gt	402294 <shortpath_dijkstra+0x158>
  402268:	b9823fa0 	ldrsw	x0, [x29, #572]
  40226c:	d37ef400 	lsl	x0, x0, #2
  402270:	9101e3a1 	add	x1, x29, #0x78
  402274:	b8606820 	ldr	w0, [x1, x0]
  402278:	7100001f 	cmp	w0, #0x0
  40227c:	540000cd 	b.le	402294 <shortpath_dijkstra+0x158>
  402280:	b94027a2 	ldr	w2, [x29, #36]
  402284:	b9823fa0 	ldrsw	x0, [x29, #572]
  402288:	d37ef400 	lsl	x0, x0, #2
  40228c:	910143a1 	add	x1, x29, #0x50
  402290:	b8206822 	str	w2, [x1, x0]
  402294:	b9823fa0 	ldrsw	x0, [x29, #572]
  402298:	d37ef400 	lsl	x0, x0, #2
  40229c:	9100a3a1 	add	x1, x29, #0x28
  4022a0:	b820683f 	str	wzr, [x1, x0]
  4022a4:	b9423fa0 	ldr	w0, [x29, #572]
  4022a8:	11000400 	add	w0, w0, #0x1
  4022ac:	b9023fa0 	str	w0, [x29, #572]
  4022b0:	b9408660 	ldr	w0, [x19, #132]
  4022b4:	b9423fa1 	ldr	w1, [x29, #572]
  4022b8:	6b00003f 	cmp	w1, w0
  4022bc:	54fffacb 	b.lt	402214 <shortpath_dijkstra+0xd8>  // b.tstop
  4022c0:	b94027a0 	ldr	w0, [x29, #36]
  4022c4:	93407c00 	sxtw	x0, w0
  4022c8:	d37ef400 	lsl	x0, x0, #2
  4022cc:	9100a3a1 	add	x1, x29, #0x28
  4022d0:	52800022 	mov	w2, #0x1                   	// #1
  4022d4:	b8206822 	str	w2, [x1, x0]
  4022d8:	b9023fbf 	str	wzr, [x29, #572]
  4022dc:	14000066 	b	402474 <shortpath_dijkstra+0x338>
  4022e0:	52807ce0 	mov	w0, #0x3e7                 	// #999
  4022e4:	b90237a0 	str	w0, [x29, #564]
  4022e8:	b94027a0 	ldr	w0, [x29, #36]
  4022ec:	b90233a0 	str	w0, [x29, #560]
  4022f0:	b9023bbf 	str	wzr, [x29, #568]
  4022f4:	14000018 	b	402354 <shortpath_dijkstra+0x218>
  4022f8:	b9823ba0 	ldrsw	x0, [x29, #568]
  4022fc:	d37ef400 	lsl	x0, x0, #2
  402300:	9100a3a1 	add	x1, x29, #0x28
  402304:	b8606820 	ldr	w0, [x1, x0]
  402308:	7100001f 	cmp	w0, #0x0
  40230c:	540001e1 	b.ne	402348 <shortpath_dijkstra+0x20c>  // b.any
  402310:	b9823ba0 	ldrsw	x0, [x29, #568]
  402314:	d37ef400 	lsl	x0, x0, #2
  402318:	9101e3a1 	add	x1, x29, #0x78
  40231c:	b8606820 	ldr	w0, [x1, x0]
  402320:	b94237a1 	ldr	w1, [x29, #564]
  402324:	6b00003f 	cmp	w1, w0
  402328:	5400010d 	b.le	402348 <shortpath_dijkstra+0x20c>
  40232c:	b9823ba0 	ldrsw	x0, [x29, #568]
  402330:	d37ef400 	lsl	x0, x0, #2
  402334:	9101e3a1 	add	x1, x29, #0x78
  402338:	b8606820 	ldr	w0, [x1, x0]
  40233c:	b90237a0 	str	w0, [x29, #564]
  402340:	b9423ba0 	ldr	w0, [x29, #568]
  402344:	b90233a0 	str	w0, [x29, #560]
  402348:	b9423ba0 	ldr	w0, [x29, #568]
  40234c:	11000400 	add	w0, w0, #0x1
  402350:	b9023ba0 	str	w0, [x29, #568]
  402354:	b9408660 	ldr	w0, [x19, #132]
  402358:	b9423ba1 	ldr	w1, [x29, #568]
  40235c:	6b00003f 	cmp	w1, w0
  402360:	54fffccb 	b.lt	4022f8 <shortpath_dijkstra+0x1bc>  // b.tstop
  402364:	b98233a0 	ldrsw	x0, [x29, #560]
  402368:	d37ef400 	lsl	x0, x0, #2
  40236c:	9100a3a1 	add	x1, x29, #0x28
  402370:	52800022 	mov	w2, #0x1                   	// #1
  402374:	b8206822 	str	w2, [x1, x0]
  402378:	b9023bbf 	str	wzr, [x29, #568]
  40237c:	14000037 	b	402458 <shortpath_dijkstra+0x31c>
  402380:	b9823ba0 	ldrsw	x0, [x29, #568]
  402384:	d37ef400 	lsl	x0, x0, #2
  402388:	9100a3a1 	add	x1, x29, #0x28
  40238c:	b8606820 	ldr	w0, [x1, x0]
  402390:	7100001f 	cmp	w0, #0x0
  402394:	540005c1 	b.ne	40244c <shortpath_dijkstra+0x310>  // b.any
  402398:	b98233a0 	ldrsw	x0, [x29, #560]
  40239c:	d37ef400 	lsl	x0, x0, #2
  4023a0:	9101e3a1 	add	x1, x29, #0x78
  4023a4:	b8606822 	ldr	w2, [x1, x0]
  4023a8:	b9823ba3 	ldrsw	x3, [x29, #568]
  4023ac:	b98233a1 	ldrsw	x1, [x29, #560]
  4023b0:	aa0103e0 	mov	x0, x1
  4023b4:	d37ef400 	lsl	x0, x0, #2
  4023b8:	8b010000 	add	x0, x0, x1
  4023bc:	d37ff800 	lsl	x0, x0, #1
  4023c0:	8b030000 	add	x0, x0, x3
  4023c4:	d37ef400 	lsl	x0, x0, #2
  4023c8:	910283a1 	add	x1, x29, #0xa0
  4023cc:	b8606820 	ldr	w0, [x1, x0]
  4023d0:	0b000041 	add	w1, w2, w0
  4023d4:	b9823ba0 	ldrsw	x0, [x29, #568]
  4023d8:	d37ef400 	lsl	x0, x0, #2
  4023dc:	9101e3a2 	add	x2, x29, #0x78
  4023e0:	b8606840 	ldr	w0, [x2, x0]
  4023e4:	6b00003f 	cmp	w1, w0
  4023e8:	5400032a 	b.ge	40244c <shortpath_dijkstra+0x310>  // b.tcont
  4023ec:	b98233a0 	ldrsw	x0, [x29, #560]
  4023f0:	d37ef400 	lsl	x0, x0, #2
  4023f4:	9101e3a1 	add	x1, x29, #0x78
  4023f8:	b8606822 	ldr	w2, [x1, x0]
  4023fc:	b9823ba3 	ldrsw	x3, [x29, #568]
  402400:	b98233a1 	ldrsw	x1, [x29, #560]
  402404:	aa0103e0 	mov	x0, x1
  402408:	d37ef400 	lsl	x0, x0, #2
  40240c:	8b010000 	add	x0, x0, x1
  402410:	d37ff800 	lsl	x0, x0, #1
  402414:	8b030000 	add	x0, x0, x3
  402418:	d37ef400 	lsl	x0, x0, #2
  40241c:	910283a1 	add	x1, x29, #0xa0
  402420:	b8606820 	ldr	w0, [x1, x0]
  402424:	0b000042 	add	w2, w2, w0
  402428:	b9823ba0 	ldrsw	x0, [x29, #568]
  40242c:	d37ef400 	lsl	x0, x0, #2
  402430:	9101e3a1 	add	x1, x29, #0x78
  402434:	b8206822 	str	w2, [x1, x0]
  402438:	b9823ba0 	ldrsw	x0, [x29, #568]
  40243c:	d37ef400 	lsl	x0, x0, #2
  402440:	910143a1 	add	x1, x29, #0x50
  402444:	b94233a2 	ldr	w2, [x29, #560]
  402448:	b8206822 	str	w2, [x1, x0]
  40244c:	b9423ba0 	ldr	w0, [x29, #568]
  402450:	11000400 	add	w0, w0, #0x1
  402454:	b9023ba0 	str	w0, [x29, #568]
  402458:	b9408660 	ldr	w0, [x19, #132]
  40245c:	b9423ba1 	ldr	w1, [x29, #568]
  402460:	6b00003f 	cmp	w1, w0
  402464:	54fff8eb 	b.lt	402380 <shortpath_dijkstra+0x244>  // b.tstop
  402468:	b9423fa0 	ldr	w0, [x29, #572]
  40246c:	11000400 	add	w0, w0, #0x1
  402470:	b9023fa0 	str	w0, [x29, #572]
  402474:	b9408660 	ldr	w0, [x19, #132]
  402478:	b9423fa1 	ldr	w1, [x29, #572]
  40247c:	6b00003f 	cmp	w1, w0
  402480:	54fff30b 	b.lt	4022e0 <shortpath_dijkstra+0x1a4>  // b.tstop
  402484:	b94027a1 	ldr	w1, [x29, #36]
  402488:	b0000000 	adrp	x0, 403000 <main+0x790>
  40248c:	910fa000 	add	x0, x0, #0x3e8
  402490:	97fff888 	bl	4006b0 <printf@plt>
  402494:	b9023fbf 	str	wzr, [x29, #572]
  402498:	14000038 	b	402578 <shortpath_dijkstra+0x43c>
  40249c:	b9823fa0 	ldrsw	x0, [x29, #572]
  4024a0:	d37ef400 	lsl	x0, x0, #2
  4024a4:	9100a3a1 	add	x1, x29, #0x28
  4024a8:	b8606820 	ldr	w0, [x1, x0]
  4024ac:	7100041f 	cmp	w0, #0x1
  4024b0:	54000461 	b.ne	40253c <shortpath_dijkstra+0x400>  // b.any
  4024b4:	b9423fa0 	ldr	w0, [x29, #572]
  4024b8:	b90233a0 	str	w0, [x29, #560]
  4024bc:	1400000d 	b	4024f0 <shortpath_dijkstra+0x3b4>
  4024c0:	b98233a0 	ldrsw	x0, [x29, #560]
  4024c4:	8b000260 	add	x0, x19, x0
  4024c8:	3941e000 	ldrb	w0, [x0, #120]
  4024cc:	2a0003e1 	mov	w1, w0
  4024d0:	b0000000 	adrp	x0, 403000 <main+0x790>
  4024d4:	9110c000 	add	x0, x0, #0x430
  4024d8:	97fff876 	bl	4006b0 <printf@plt>
  4024dc:	b98233a0 	ldrsw	x0, [x29, #560]
  4024e0:	d37ef400 	lsl	x0, x0, #2
  4024e4:	910143a1 	add	x1, x29, #0x50
  4024e8:	b8606820 	ldr	w0, [x1, x0]
  4024ec:	b90233a0 	str	w0, [x29, #560]
  4024f0:	b94027a0 	ldr	w0, [x29, #36]
  4024f4:	b94233a1 	ldr	w1, [x29, #560]
  4024f8:	6b00003f 	cmp	w1, w0
  4024fc:	54fffe21 	b.ne	4024c0 <shortpath_dijkstra+0x384>  // b.any
  402500:	b98233a0 	ldrsw	x0, [x29, #560]
  402504:	8b000260 	add	x0, x19, x0
  402508:	3941e000 	ldrb	w0, [x0, #120]
  40250c:	2a0003e1 	mov	w1, w0
  402510:	b0000000 	adrp	x0, 403000 <main+0x790>
  402514:	9109c000 	add	x0, x0, #0x270
  402518:	97fff866 	bl	4006b0 <printf@plt>
  40251c:	b9823fa0 	ldrsw	x0, [x29, #572]
  402520:	d37ef400 	lsl	x0, x0, #2
  402524:	910143a1 	add	x1, x29, #0x50
  402528:	b8606821 	ldr	w1, [x1, x0]
  40252c:	b0000000 	adrp	x0, 403000 <main+0x790>
  402530:	9110e000 	add	x0, x0, #0x438
  402534:	97fff85f 	bl	4006b0 <printf@plt>
  402538:	1400000d 	b	40256c <shortpath_dijkstra+0x430>
  40253c:	b9823fa0 	ldrsw	x0, [x29, #572]
  402540:	8b000260 	add	x0, x19, x0
  402544:	3941e000 	ldrb	w0, [x0, #120]
  402548:	2a0003e1 	mov	w1, w0
  40254c:	b94027a0 	ldr	w0, [x29, #36]
  402550:	93407c00 	sxtw	x0, w0
  402554:	8b000260 	add	x0, x19, x0
  402558:	3941e000 	ldrb	w0, [x0, #120]
  40255c:	2a0003e2 	mov	w2, w0
  402560:	b0000000 	adrp	x0, 403000 <main+0x790>
  402564:	91110000 	add	x0, x0, #0x440
  402568:	97fff852 	bl	4006b0 <printf@plt>
  40256c:	b9423fa0 	ldr	w0, [x29, #572]
  402570:	11000400 	add	w0, w0, #0x1
  402574:	b9023fa0 	str	w0, [x29, #572]
  402578:	b9408660 	ldr	w0, [x19, #132]
  40257c:	b9423fa1 	ldr	w1, [x29, #572]
  402580:	6b00003f 	cmp	w1, w0
  402584:	54fff8cb 	b.lt	40249c <shortpath_dijkstra+0x360>  // b.tstop
  402588:	d503201f 	nop
  40258c:	f9400bf3 	ldr	x19, [sp, #16]
  402590:	a9407bfd 	ldp	x29, x30, [sp]
  402594:	910903ff 	add	sp, sp, #0x240
  402598:	d65f03c0 	ret

000000000040259c <shortpath_floyd>:
  40259c:	d10d43ff 	sub	sp, sp, #0x350
  4025a0:	a9007bfd 	stp	x29, x30, [sp]
  4025a4:	910003fd 	mov	x29, sp
  4025a8:	f9000bf3 	str	x19, [sp, #16]
  4025ac:	aa0003f3 	mov	x19, x0
  4025b0:	b9034fbf 	str	wzr, [x29, #844]
  4025b4:	1400002a 	b	40265c <shortpath_floyd+0xc0>
  4025b8:	b9034bbf 	str	wzr, [x29, #840]
  4025bc:	14000021 	b	402640 <shortpath_floyd+0xa4>
  4025c0:	b9834ba2 	ldrsw	x2, [x29, #840]
  4025c4:	b9834fa1 	ldrsw	x1, [x29, #844]
  4025c8:	aa0103e0 	mov	x0, x1
  4025cc:	d37ef400 	lsl	x0, x0, #2
  4025d0:	8b010000 	add	x0, x0, x1
  4025d4:	d37ff800 	lsl	x0, x0, #1
  4025d8:	8b020000 	add	x0, x0, x2
  4025dc:	91009000 	add	x0, x0, #0x24
  4025e0:	b8607a62 	ldr	w2, [x19, x0, lsl #2]
  4025e4:	b9834ba3 	ldrsw	x3, [x29, #840]
  4025e8:	b9834fa1 	ldrsw	x1, [x29, #844]
  4025ec:	aa0103e0 	mov	x0, x1
  4025f0:	d37ef400 	lsl	x0, x0, #2
  4025f4:	8b010000 	add	x0, x0, x1
  4025f8:	d37ff800 	lsl	x0, x0, #1
  4025fc:	8b030000 	add	x0, x0, x3
  402600:	d37ef400 	lsl	x0, x0, #2
  402604:	910083a1 	add	x1, x29, #0x20
  402608:	b8206822 	str	w2, [x1, x0]
  40260c:	b9834ba2 	ldrsw	x2, [x29, #840]
  402610:	b9834fa1 	ldrsw	x1, [x29, #844]
  402614:	aa0103e0 	mov	x0, x1
  402618:	d37ef400 	lsl	x0, x0, #2
  40261c:	8b010000 	add	x0, x0, x1
  402620:	d37ff800 	lsl	x0, x0, #1
  402624:	8b020000 	add	x0, x0, x2
  402628:	d37ef400 	lsl	x0, x0, #2
  40262c:	9106c3a1 	add	x1, x29, #0x1b0
  402630:	b820683f 	str	wzr, [x1, x0]
  402634:	b9434ba0 	ldr	w0, [x29, #840]
  402638:	11000400 	add	w0, w0, #0x1
  40263c:	b9034ba0 	str	w0, [x29, #840]
  402640:	b9408660 	ldr	w0, [x19, #132]
  402644:	b9434ba1 	ldr	w1, [x29, #840]
  402648:	6b00003f 	cmp	w1, w0
  40264c:	54fffbab 	b.lt	4025c0 <shortpath_floyd+0x24>  // b.tstop
  402650:	b9434fa0 	ldr	w0, [x29, #844]
  402654:	11000400 	add	w0, w0, #0x1
  402658:	b9034fa0 	str	w0, [x29, #844]
  40265c:	b9408660 	ldr	w0, [x19, #132]
  402660:	b9434fa1 	ldr	w1, [x29, #844]
  402664:	6b00003f 	cmp	w1, w0
  402668:	54fffa8b 	b.lt	4025b8 <shortpath_floyd+0x1c>  // b.tstop
  40266c:	b0000000 	adrp	x0, 403000 <main+0x790>
  402670:	91116000 	add	x0, x0, #0x458
  402674:	97fff803 	bl	400680 <puts@plt>
  402678:	b90347bf 	str	wzr, [x29, #836]
  40267c:	14000074 	b	40284c <shortpath_floyd+0x2b0>
  402680:	b9034fbf 	str	wzr, [x29, #844]
  402684:	1400006b 	b	402830 <shortpath_floyd+0x294>
  402688:	b9834ba2 	ldrsw	x2, [x29, #840]
  40268c:	b9834fa1 	ldrsw	x1, [x29, #844]
  402690:	aa0103e0 	mov	x0, x1
  402694:	d37ef400 	lsl	x0, x0, #2
  402698:	8b010000 	add	x0, x0, x1
  40269c:	d37ff800 	lsl	x0, x0, #1
  4026a0:	8b020000 	add	x0, x0, x2
  4026a4:	d37ef400 	lsl	x0, x0, #2
  4026a8:	910083a1 	add	x1, x29, #0x20
  4026ac:	b8606822 	ldr	w2, [x1, x0]
  4026b0:	b98347a3 	ldrsw	x3, [x29, #836]
  4026b4:	b9834fa1 	ldrsw	x1, [x29, #844]
  4026b8:	aa0103e0 	mov	x0, x1
  4026bc:	d37ef400 	lsl	x0, x0, #2
  4026c0:	8b010000 	add	x0, x0, x1
  4026c4:	d37ff800 	lsl	x0, x0, #1
  4026c8:	8b030000 	add	x0, x0, x3
  4026cc:	d37ef400 	lsl	x0, x0, #2
  4026d0:	910083a1 	add	x1, x29, #0x20
  4026d4:	b8606823 	ldr	w3, [x1, x0]
  4026d8:	b9834ba4 	ldrsw	x4, [x29, #840]
  4026dc:	b98347a1 	ldrsw	x1, [x29, #836]
  4026e0:	aa0103e0 	mov	x0, x1
  4026e4:	d37ef400 	lsl	x0, x0, #2
  4026e8:	8b010000 	add	x0, x0, x1
  4026ec:	d37ff800 	lsl	x0, x0, #1
  4026f0:	8b040000 	add	x0, x0, x4
  4026f4:	d37ef400 	lsl	x0, x0, #2
  4026f8:	910083a1 	add	x1, x29, #0x20
  4026fc:	b8606820 	ldr	w0, [x1, x0]
  402700:	0b000060 	add	w0, w3, w0
  402704:	6b00005f 	cmp	w2, w0
  402708:	5400056d 	b.le	4027b4 <shortpath_floyd+0x218>
  40270c:	b98347a2 	ldrsw	x2, [x29, #836]
  402710:	b9834fa1 	ldrsw	x1, [x29, #844]
  402714:	aa0103e0 	mov	x0, x1
  402718:	d37ef400 	lsl	x0, x0, #2
  40271c:	8b010000 	add	x0, x0, x1
  402720:	d37ff800 	lsl	x0, x0, #1
  402724:	8b020000 	add	x0, x0, x2
  402728:	d37ef400 	lsl	x0, x0, #2
  40272c:	910083a1 	add	x1, x29, #0x20
  402730:	b8606822 	ldr	w2, [x1, x0]
  402734:	b9834ba3 	ldrsw	x3, [x29, #840]
  402738:	b98347a1 	ldrsw	x1, [x29, #836]
  40273c:	aa0103e0 	mov	x0, x1
  402740:	d37ef400 	lsl	x0, x0, #2
  402744:	8b010000 	add	x0, x0, x1
  402748:	d37ff800 	lsl	x0, x0, #1
  40274c:	8b030000 	add	x0, x0, x3
  402750:	d37ef400 	lsl	x0, x0, #2
  402754:	910083a1 	add	x1, x29, #0x20
  402758:	b8606820 	ldr	w0, [x1, x0]
  40275c:	0b000042 	add	w2, w2, w0
  402760:	b9834ba3 	ldrsw	x3, [x29, #840]
  402764:	b9834fa1 	ldrsw	x1, [x29, #844]
  402768:	aa0103e0 	mov	x0, x1
  40276c:	d37ef400 	lsl	x0, x0, #2
  402770:	8b010000 	add	x0, x0, x1
  402774:	d37ff800 	lsl	x0, x0, #1
  402778:	8b030000 	add	x0, x0, x3
  40277c:	d37ef400 	lsl	x0, x0, #2
  402780:	910083a1 	add	x1, x29, #0x20
  402784:	b8206822 	str	w2, [x1, x0]
  402788:	b9834ba2 	ldrsw	x2, [x29, #840]
  40278c:	b9834fa1 	ldrsw	x1, [x29, #844]
  402790:	aa0103e0 	mov	x0, x1
  402794:	d37ef400 	lsl	x0, x0, #2
  402798:	8b010000 	add	x0, x0, x1
  40279c:	d37ff800 	lsl	x0, x0, #1
  4027a0:	8b020000 	add	x0, x0, x2
  4027a4:	d37ef400 	lsl	x0, x0, #2
  4027a8:	9106c3a1 	add	x1, x29, #0x1b0
  4027ac:	b94347a2 	ldr	w2, [x29, #836]
  4027b0:	b8206822 	str	w2, [x1, x0]
  4027b4:	b9434fa0 	ldr	w0, [x29, #844]
  4027b8:	51000400 	sub	w0, w0, #0x1
  4027bc:	93407c00 	sxtw	x0, w0
  4027c0:	8b000260 	add	x0, x19, x0
  4027c4:	3941e000 	ldrb	w0, [x0, #120]
  4027c8:	2a0003e4 	mov	w4, w0
  4027cc:	b9434ba0 	ldr	w0, [x29, #840]
  4027d0:	51000400 	sub	w0, w0, #0x1
  4027d4:	93407c00 	sxtw	x0, w0
  4027d8:	8b000260 	add	x0, x19, x0
  4027dc:	3941e000 	ldrb	w0, [x0, #120]
  4027e0:	2a0003e5 	mov	w5, w0
  4027e4:	b9834ba2 	ldrsw	x2, [x29, #840]
  4027e8:	b9834fa1 	ldrsw	x1, [x29, #844]
  4027ec:	aa0103e0 	mov	x0, x1
  4027f0:	d37ef400 	lsl	x0, x0, #2
  4027f4:	8b010000 	add	x0, x0, x1
  4027f8:	d37ff800 	lsl	x0, x0, #1
  4027fc:	8b020000 	add	x0, x0, x2
  402800:	d37ef400 	lsl	x0, x0, #2
  402804:	910083a1 	add	x1, x29, #0x20
  402808:	b8606821 	ldr	w1, [x1, x0]
  40280c:	b0000000 	adrp	x0, 403000 <main+0x790>
  402810:	91120000 	add	x0, x0, #0x480
  402814:	2a0103e3 	mov	w3, w1
  402818:	2a0503e2 	mov	w2, w5
  40281c:	2a0403e1 	mov	w1, w4
  402820:	97fff7a4 	bl	4006b0 <printf@plt>
  402824:	b9434fa0 	ldr	w0, [x29, #844]
  402828:	11000400 	add	w0, w0, #0x1
  40282c:	b9034fa0 	str	w0, [x29, #844]
  402830:	b9408660 	ldr	w0, [x19, #132]
  402834:	b9434fa1 	ldr	w1, [x29, #844]
  402838:	6b00003f 	cmp	w1, w0
  40283c:	54fff26b 	b.lt	402688 <shortpath_floyd+0xec>  // b.tstop
  402840:	b94347a0 	ldr	w0, [x29, #836]
  402844:	11000400 	add	w0, w0, #0x1
  402848:	b90347a0 	str	w0, [x29, #836]
  40284c:	b9408660 	ldr	w0, [x19, #132]
  402850:	b94347a1 	ldr	w1, [x29, #836]
  402854:	6b00003f 	cmp	w1, w0
  402858:	54fff14b 	b.lt	402680 <shortpath_floyd+0xe4>  // b.tstop
  40285c:	d503201f 	nop
  402860:	f9400bf3 	ldr	x19, [sp, #16]
  402864:	a9407bfd 	ldp	x29, x30, [sp]
  402868:	910d43ff 	add	sp, sp, #0x350
  40286c:	d65f03c0 	ret

0000000000402870 <main>:
  402870:	d11203ff 	sub	sp, sp, #0x480
  402874:	a9007bfd 	stp	x29, x30, [sp]
  402878:	910003fd 	mov	x29, sp
  40287c:	f9000bf3 	str	x19, [sp, #16]
  402880:	b0000000 	adrp	x0, 403000 <main+0x790>
  402884:	91126000 	add	x0, x0, #0x498
  402888:	97fff78a 	bl	4006b0 <printf@plt>
  40288c:	9111e3a1 	add	x1, x29, #0x478
  402890:	b0000000 	adrp	x0, 403000 <main+0x790>
  402894:	910f8000 	add	x0, x0, #0x3e0
  402898:	97fff782 	bl	4006a0 <__isoc99_scanf@plt>
  40289c:	b9447ba1 	ldr	w1, [x29, #1144]
  4028a0:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  4028a4:	91032000 	add	x0, x0, #0xc8
  4028a8:	b9008c01 	str	w1, [x0, #140]
  4028ac:	b9447ba1 	ldr	w1, [x29, #1144]
  4028b0:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  4028b4:	910be000 	add	x0, x0, #0x2f8
  4028b8:	b900a801 	str	w1, [x0, #168]
  4028bc:	b0000000 	adrp	x0, 403000 <main+0x790>
  4028c0:	9113a000 	add	x0, x0, #0x4e8
  4028c4:	97fff77b 	bl	4006b0 <printf@plt>
  4028c8:	9111d3a2 	add	x2, x29, #0x474
  4028cc:	9111e3a1 	add	x1, x29, #0x478
  4028d0:	b0000000 	adrp	x0, 403000 <main+0x790>
  4028d4:	91140000 	add	x0, x0, #0x500
  4028d8:	97fff772 	bl	4006a0 <__isoc99_scanf@plt>
  4028dc:	b9447ba1 	ldr	w1, [x29, #1144]
  4028e0:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  4028e4:	91032000 	add	x0, x0, #0xc8
  4028e8:	b9008401 	str	w1, [x0, #132]
  4028ec:	b9447ba1 	ldr	w1, [x29, #1144]
  4028f0:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  4028f4:	910be000 	add	x0, x0, #0x2f8
  4028f8:	b900a001 	str	w1, [x0, #160]
  4028fc:	b94477a1 	ldr	w1, [x29, #1140]
  402900:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402904:	91032000 	add	x0, x0, #0xc8
  402908:	b9008801 	str	w1, [x0, #136]
  40290c:	b94477a1 	ldr	w1, [x29, #1140]
  402910:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402914:	910be000 	add	x0, x0, #0x2f8
  402918:	b900a401 	str	w1, [x0, #164]
  40291c:	b9047bbf 	str	wzr, [x29, #1144]
  402920:	1400002f 	b	4029dc <main+0x16c>
  402924:	b9447ba0 	ldr	w0, [x29, #1144]
  402928:	11000401 	add	w1, w0, #0x1
  40292c:	b0000000 	adrp	x0, 403000 <main+0x790>
  402930:	91142000 	add	x0, x0, #0x508
  402934:	97fff75f 	bl	4006b0 <printf@plt>
  402938:	b9447ba0 	ldr	w0, [x29, #1144]
  40293c:	93407c00 	sxtw	x0, w0
  402940:	9101c001 	add	x1, x0, #0x70
  402944:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402948:	91032000 	add	x0, x0, #0xc8
  40294c:	8b000020 	add	x0, x1, x0
  402950:	91002001 	add	x1, x0, #0x8
  402954:	b0000000 	adrp	x0, 403000 <main+0x790>
  402958:	9114a000 	add	x0, x0, #0x528
  40295c:	97fff751 	bl	4006a0 <__isoc99_scanf@plt>
  402960:	b9447ba2 	ldr	w2, [x29, #1144]
  402964:	b9447ba3 	ldr	w3, [x29, #1144]
  402968:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  40296c:	91032001 	add	x1, x0, #0xc8
  402970:	93407c40 	sxtw	x0, w2
  402974:	8b000020 	add	x0, x1, x0
  402978:	3941e002 	ldrb	w2, [x0, #120]
  40297c:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402980:	910be001 	add	x1, x0, #0x2f8
  402984:	93407c60 	sxtw	x0, w3
  402988:	d37cec00 	lsl	x0, x0, #4
  40298c:	8b000020 	add	x0, x1, x0
  402990:	2a0203e1 	mov	w1, w2
  402994:	39001001 	strb	w1, [x0, #4]
  402998:	b9447ba2 	ldr	w2, [x29, #1144]
  40299c:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  4029a0:	910be001 	add	x1, x0, #0x2f8
  4029a4:	93407c40 	sxtw	x0, w2
  4029a8:	d37cec00 	lsl	x0, x0, #4
  4029ac:	8b000020 	add	x0, x1, x0
  4029b0:	f900041f 	str	xzr, [x0, #8]
  4029b4:	b9447ba2 	ldr	w2, [x29, #1144]
  4029b8:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  4029bc:	910be001 	add	x1, x0, #0x2f8
  4029c0:	93407c40 	sxtw	x0, w2
  4029c4:	d37cec00 	lsl	x0, x0, #4
  4029c8:	8b000020 	add	x0, x1, x0
  4029cc:	b900001f 	str	wzr, [x0]
  4029d0:	b9447ba0 	ldr	w0, [x29, #1144]
  4029d4:	11000400 	add	w0, w0, #0x1
  4029d8:	b9047ba0 	str	w0, [x29, #1144]
  4029dc:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  4029e0:	91032000 	add	x0, x0, #0xc8
  4029e4:	b9408401 	ldr	w1, [x0, #132]
  4029e8:	b9447ba0 	ldr	w0, [x29, #1144]
  4029ec:	6b00003f 	cmp	w1, w0
  4029f0:	54fff9ac 	b.gt	402924 <main+0xb4>
  4029f4:	52800020 	mov	w0, #0x1                   	// #1
  4029f8:	b90473a0 	str	w0, [x29, #1136]
  4029fc:	14000074 	b	402bcc <main+0x35c>
  402a00:	d503201f 	nop
  402a04:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402a08:	91032000 	add	x0, x0, #0xc8
  402a0c:	b9408c00 	ldr	w0, [x0, #140]
  402a10:	7100041f 	cmp	w0, #0x1
  402a14:	540000c0 	b.eq	402a2c <main+0x1bc>  // b.none
  402a18:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402a1c:	91032000 	add	x0, x0, #0xc8
  402a20:	b9408c00 	ldr	w0, [x0, #140]
  402a24:	71000c1f 	cmp	w0, #0x3
  402a28:	540000c1 	b.ne	402a40 <main+0x1d0>  // b.any
  402a2c:	b94473a1 	ldr	w1, [x29, #1136]
  402a30:	b0000000 	adrp	x0, 403000 <main+0x790>
  402a34:	9114c000 	add	x0, x0, #0x530
  402a38:	97fff71e 	bl	4006b0 <printf@plt>
  402a3c:	14000005 	b	402a50 <main+0x1e0>
  402a40:	b94473a1 	ldr	w1, [x29, #1136]
  402a44:	b0000000 	adrp	x0, 403000 <main+0x790>
  402a48:	91158000 	add	x0, x0, #0x560
  402a4c:	97fff719 	bl	4006b0 <printf@plt>
  402a50:	9111d3a2 	add	x2, x29, #0x474
  402a54:	9111e3a1 	add	x1, x29, #0x478
  402a58:	b0000000 	adrp	x0, 403000 <main+0x790>
  402a5c:	91140000 	add	x0, x0, #0x500
  402a60:	97fff710 	bl	4006a0 <__isoc99_scanf@plt>
  402a64:	b94473a0 	ldr	w0, [x29, #1136]
  402a68:	51000401 	sub	w1, w0, #0x1
  402a6c:	b9447ba2 	ldr	w2, [x29, #1144]
  402a70:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402a74:	91032000 	add	x0, x0, #0xc8
  402a78:	93407c21 	sxtw	x1, w1
  402a7c:	b8217802 	str	w2, [x0, x1, lsl #2]
  402a80:	b94473a0 	ldr	w0, [x29, #1136]
  402a84:	51000403 	sub	w3, w0, #0x1
  402a88:	b94477a1 	ldr	w1, [x29, #1140]
  402a8c:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402a90:	91032002 	add	x2, x0, #0xc8
  402a94:	93407c60 	sxtw	x0, w3
  402a98:	91002000 	add	x0, x0, #0x8
  402a9c:	d37ef400 	lsl	x0, x0, #2
  402aa0:	8b000040 	add	x0, x2, x0
  402aa4:	b9000801 	str	w1, [x0, #8]
  402aa8:	d503201f 	nop
  402aac:	b9447ba0 	ldr	w0, [x29, #1144]
  402ab0:	7100001f 	cmp	w0, #0x0
  402ab4:	540000ac 	b.gt	402ac8 <main+0x258>
  402ab8:	b0000000 	adrp	x0, 403000 <main+0x790>
  402abc:	91166000 	add	x0, x0, #0x598
  402ac0:	97fff6fc 	bl	4006b0 <printf@plt>
  402ac4:	17ffffd0 	b	402a04 <main+0x194>
  402ac8:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402acc:	91032000 	add	x0, x0, #0xc8
  402ad0:	b9408401 	ldr	w1, [x0, #132]
  402ad4:	b9447ba0 	ldr	w0, [x29, #1144]
  402ad8:	6b00003f 	cmp	w1, w0
  402adc:	54fffeeb 	b.lt	402ab8 <main+0x248>  // b.tstop
  402ae0:	b94477a0 	ldr	w0, [x29, #1140]
  402ae4:	7100001f 	cmp	w0, #0x0
  402ae8:	54fffe8d 	b.le	402ab8 <main+0x248>
  402aec:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402af0:	91032000 	add	x0, x0, #0xc8
  402af4:	b9408401 	ldr	w1, [x0, #132]
  402af8:	b94477a0 	ldr	w0, [x29, #1140]
  402afc:	6b00003f 	cmp	w1, w0
  402b00:	54fffdcb 	b.lt	402ab8 <main+0x248>  // b.tstop
  402b04:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402b08:	91032000 	add	x0, x0, #0xc8
  402b0c:	b9408c00 	ldr	w0, [x0, #140]
  402b10:	71000c1f 	cmp	w0, #0x3
  402b14:	540000c0 	b.eq	402b2c <main+0x2bc>  // b.none
  402b18:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402b1c:	91032000 	add	x0, x0, #0xc8
  402b20:	b9408c00 	ldr	w0, [x0, #140]
  402b24:	7100101f 	cmp	w0, #0x4
  402b28:	54000221 	b.ne	402b6c <main+0x2fc>  // b.any
  402b2c:	b0000000 	adrp	x0, 403000 <main+0x790>
  402b30:	91170000 	add	x0, x0, #0x5c0
  402b34:	97fff6df 	bl	4006b0 <printf@plt>
  402b38:	9111b3a1 	add	x1, x29, #0x46c
  402b3c:	b0000000 	adrp	x0, 403000 <main+0x790>
  402b40:	910f8000 	add	x0, x0, #0x3e0
  402b44:	97fff6d7 	bl	4006a0 <__isoc99_scanf@plt>
  402b48:	b94473a0 	ldr	w0, [x29, #1136]
  402b4c:	51000401 	sub	w1, w0, #0x1
  402b50:	b9446fa2 	ldr	w2, [x29, #1132]
  402b54:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402b58:	91032000 	add	x0, x0, #0xc8
  402b5c:	93407c21 	sxtw	x1, w1
  402b60:	91005021 	add	x1, x1, #0x14
  402b64:	b8217802 	str	w2, [x0, x1, lsl #2]
  402b68:	14000008 	b	402b88 <main+0x318>
  402b6c:	b94473a0 	ldr	w0, [x29, #1136]
  402b70:	51000401 	sub	w1, w0, #0x1
  402b74:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402b78:	91032000 	add	x0, x0, #0xc8
  402b7c:	93407c21 	sxtw	x1, w1
  402b80:	91005021 	add	x1, x1, #0x14
  402b84:	b821781f 	str	wzr, [x0, x1, lsl #2]
  402b88:	b9447ba3 	ldr	w3, [x29, #1144]
  402b8c:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402b90:	910be001 	add	x1, x0, #0x2f8
  402b94:	93407c60 	sxtw	x0, w3
  402b98:	d37cec00 	lsl	x0, x0, #4
  402b9c:	8b000020 	add	x0, x1, x0
  402ba0:	b9400000 	ldr	w0, [x0]
  402ba4:	11000401 	add	w1, w0, #0x1
  402ba8:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402bac:	910be002 	add	x2, x0, #0x2f8
  402bb0:	93407c60 	sxtw	x0, w3
  402bb4:	d37cec00 	lsl	x0, x0, #4
  402bb8:	8b000040 	add	x0, x2, x0
  402bbc:	b9000001 	str	w1, [x0]
  402bc0:	b94473a0 	ldr	w0, [x29, #1136]
  402bc4:	11000400 	add	w0, w0, #0x1
  402bc8:	b90473a0 	str	w0, [x29, #1136]
  402bcc:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402bd0:	91032000 	add	x0, x0, #0xc8
  402bd4:	b9408801 	ldr	w1, [x0, #136]
  402bd8:	b94473a0 	ldr	w0, [x29, #1136]
  402bdc:	6b00003f 	cmp	w1, w0
  402be0:	54fff10a 	b.ge	402a00 <main+0x190>  // b.tcont
  402be4:	d503201f 	nop
  402be8:	b0000000 	adrp	x0, 403000 <main+0x790>
  402bec:	91176000 	add	x0, x0, #0x5d8
  402bf0:	97fff6a4 	bl	400680 <puts@plt>
  402bf4:	b0000000 	adrp	x0, 403000 <main+0x790>
  402bf8:	9117c000 	add	x0, x0, #0x5f0
  402bfc:	97fff6a1 	bl	400680 <puts@plt>
  402c00:	b0000000 	adrp	x0, 403000 <main+0x790>
  402c04:	91180000 	add	x0, x0, #0x600
  402c08:	97fff69e 	bl	400680 <puts@plt>
  402c0c:	b0000000 	adrp	x0, 403000 <main+0x790>
  402c10:	91182000 	add	x0, x0, #0x608
  402c14:	97fff69b 	bl	400680 <puts@plt>
  402c18:	b0000000 	adrp	x0, 403000 <main+0x790>
  402c1c:	91184000 	add	x0, x0, #0x610
  402c20:	97fff698 	bl	400680 <puts@plt>
  402c24:	b0000000 	adrp	x0, 403000 <main+0x790>
  402c28:	9118c000 	add	x0, x0, #0x630
  402c2c:	97fff695 	bl	400680 <puts@plt>
  402c30:	b0000000 	adrp	x0, 403000 <main+0x790>
  402c34:	91192000 	add	x0, x0, #0x648
  402c38:	97fff692 	bl	400680 <puts@plt>
  402c3c:	b0000000 	adrp	x0, 403000 <main+0x790>
  402c40:	91198000 	add	x0, x0, #0x660
  402c44:	97fff68f 	bl	400680 <puts@plt>
  402c48:	b0000000 	adrp	x0, 403000 <main+0x790>
  402c4c:	911aa000 	add	x0, x0, #0x6a8
  402c50:	97fff68c 	bl	400680 <puts@plt>
  402c54:	b0000000 	adrp	x0, 403000 <main+0x790>
  402c58:	911b8000 	add	x0, x0, #0x6e0
  402c5c:	97fff695 	bl	4006b0 <printf@plt>
  402c60:	9111f3a1 	add	x1, x29, #0x47c
  402c64:	b0000000 	adrp	x0, 403000 <main+0x790>
  402c68:	910f8000 	add	x0, x0, #0x3e0
  402c6c:	97fff68d 	bl	4006a0 <__isoc99_scanf@plt>
  402c70:	b9447fa0 	ldr	w0, [x29, #1148]
  402c74:	7100141f 	cmp	w0, #0x5
  402c78:	540012a0 	b.eq	402ecc <main+0x65c>  // b.none
  402c7c:	7100141f 	cmp	w0, #0x5
  402c80:	540001ac 	b.gt	402cb4 <main+0x444>
  402c84:	7100081f 	cmp	w0, #0x2
  402c88:	540003e0 	b.eq	402d04 <main+0x494>  // b.none
  402c8c:	7100081f 	cmp	w0, #0x2
  402c90:	5400008c 	b.gt	402ca0 <main+0x430>
  402c94:	7100041f 	cmp	w0, #0x1
  402c98:	54000200 	b.eq	402cd8 <main+0x468>  // b.none
  402c9c:	14000143 	b	4031a8 <main+0x938>
  402ca0:	71000c1f 	cmp	w0, #0x3
  402ca4:	540005c0 	b.eq	402d5c <main+0x4ec>  // b.none
  402ca8:	7100101f 	cmp	w0, #0x4
  402cac:	54000b40 	b.eq	402e14 <main+0x5a4>  // b.none
  402cb0:	1400013e 	b	4031a8 <main+0x938>
  402cb4:	71001c1f 	cmp	w0, #0x7
  402cb8:	54001a60 	b.eq	403004 <main+0x794>  // b.none
  402cbc:	71001c1f 	cmp	w0, #0x7
  402cc0:	5400146b 	b.lt	402f4c <main+0x6dc>  // b.tstop
  402cc4:	7100201f 	cmp	w0, #0x8
  402cc8:	54001f00 	b.eq	4030a8 <main+0x838>  // b.none
  402ccc:	7100241f 	cmp	w0, #0x9
  402cd0:	540022c0 	b.eq	403128 <main+0x8b8>  // b.none
  402cd4:	14000135 	b	4031a8 <main+0x938>
  402cd8:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402cdc:	91032001 	add	x1, x0, #0xc8
  402ce0:	910903a0 	add	x0, x29, #0x240
  402ce4:	aa0103e3 	mov	x3, x1
  402ce8:	d2804401 	mov	x1, #0x220                 	// #544
  402cec:	aa0103e2 	mov	x2, x1
  402cf0:	aa0303e1 	mov	x1, x3
  402cf4:	97fff64f 	bl	400630 <memcpy@plt>
  402cf8:	910903a0 	add	x0, x29, #0x240
  402cfc:	97fff86c 	bl	400eac <creategraph>
  402d00:	1400012d 	b	4031b4 <main+0x944>
  402d04:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402d08:	91032001 	add	x1, x0, #0xc8
  402d0c:	910083a0 	add	x0, x29, #0x20
  402d10:	aa0103e3 	mov	x3, x1
  402d14:	d2804401 	mov	x1, #0x220                 	// #544
  402d18:	aa0103e2 	mov	x2, x1
  402d1c:	aa0303e1 	mov	x1, x3
  402d20:	97fff644 	bl	400630 <memcpy@plt>
  402d24:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402d28:	910be001 	add	x1, x0, #0x2f8
  402d2c:	910bc3a0 	add	x0, x29, #0x2f0
  402d30:	aa0103e3 	mov	x3, x1
  402d34:	d2801601 	mov	x1, #0xb0                  	// #176
  402d38:	aa0103e2 	mov	x2, x1
  402d3c:	aa0303e1 	mov	x1, x3
  402d40:	97fff63c 	bl	400630 <memcpy@plt>
  402d44:	910bc3a1 	add	x1, x29, #0x2f0
  402d48:	910083a0 	add	x0, x29, #0x20
  402d4c:	910903a2 	add	x2, x29, #0x240
  402d50:	aa0203e8 	mov	x8, x2
  402d54:	97fff898 	bl	400fb4 <createlist>
  402d58:	14000117 	b	4031b4 <main+0x944>
  402d5c:	b0000000 	adrp	x0, 403000 <main+0x790>
  402d60:	911c0000 	add	x0, x0, #0x700
  402d64:	97fff653 	bl	4006b0 <printf@plt>
  402d68:	9111c3a1 	add	x1, x29, #0x470
  402d6c:	b0000000 	adrp	x0, 403000 <main+0x790>
  402d70:	910f8000 	add	x0, x0, #0x3e0
  402d74:	97fff64b 	bl	4006a0 <__isoc99_scanf@plt>
  402d78:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402d7c:	91032001 	add	x1, x0, #0xc8
  402d80:	910343a0 	add	x0, x29, #0xd0
  402d84:	aa0103e3 	mov	x3, x1
  402d88:	d2804401 	mov	x1, #0x220                 	// #544
  402d8c:	aa0103e2 	mov	x2, x1
  402d90:	aa0303e1 	mov	x1, x3
  402d94:	97fff627 	bl	400630 <memcpy@plt>
  402d98:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402d9c:	910be001 	add	x1, x0, #0x2f8
  402da0:	910bc3a0 	add	x0, x29, #0x2f0
  402da4:	aa0103e3 	mov	x3, x1
  402da8:	d2801601 	mov	x1, #0xb0                  	// #176
  402dac:	aa0103e2 	mov	x2, x1
  402db0:	aa0303e1 	mov	x1, x3
  402db4:	97fff61f 	bl	400630 <memcpy@plt>
  402db8:	910bc3a1 	add	x1, x29, #0x2f0
  402dbc:	910343a0 	add	x0, x29, #0xd0
  402dc0:	910083a2 	add	x2, x29, #0x20
  402dc4:	aa0203e8 	mov	x8, x2
  402dc8:	97fff87b 	bl	400fb4 <createlist>
  402dcc:	b94473a1 	ldr	w1, [x29, #1136]
  402dd0:	b0000000 	adrp	x0, 403000 <main+0x790>
  402dd4:	911c2000 	add	x0, x0, #0x708
  402dd8:	97fff636 	bl	4006b0 <printf@plt>
  402ddc:	b94473b3 	ldr	w19, [x29, #1136]
  402de0:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402de4:	910be001 	add	x1, x0, #0x2f8
  402de8:	910083a0 	add	x0, x29, #0x20
  402dec:	aa0103e3 	mov	x3, x1
  402df0:	d2801601 	mov	x1, #0xb0                  	// #176
  402df4:	aa0103e2 	mov	x2, x1
  402df8:	aa0303e1 	mov	x1, x3
  402dfc:	97fff60d 	bl	400630 <memcpy@plt>
  402e00:	910083a0 	add	x0, x29, #0x20
  402e04:	aa0003e1 	mov	x1, x0
  402e08:	2a1303e0 	mov	w0, w19
  402e0c:	97fff997 	bl	401468 <dfs>
  402e10:	140000e9 	b	4031b4 <main+0x944>
  402e14:	b0000000 	adrp	x0, 403000 <main+0x790>
  402e18:	911c8000 	add	x0, x0, #0x720
  402e1c:	97fff625 	bl	4006b0 <printf@plt>
  402e20:	9111c3a1 	add	x1, x29, #0x470
  402e24:	b0000000 	adrp	x0, 403000 <main+0x790>
  402e28:	910f8000 	add	x0, x0, #0x3e0
  402e2c:	97fff61d 	bl	4006a0 <__isoc99_scanf@plt>
  402e30:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402e34:	91032001 	add	x1, x0, #0xc8
  402e38:	910343a0 	add	x0, x29, #0xd0
  402e3c:	aa0103e3 	mov	x3, x1
  402e40:	d2804401 	mov	x1, #0x220                 	// #544
  402e44:	aa0103e2 	mov	x2, x1
  402e48:	aa0303e1 	mov	x1, x3
  402e4c:	97fff5f9 	bl	400630 <memcpy@plt>
  402e50:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402e54:	910be001 	add	x1, x0, #0x2f8
  402e58:	910bc3a0 	add	x0, x29, #0x2f0
  402e5c:	aa0103e3 	mov	x3, x1
  402e60:	d2801601 	mov	x1, #0xb0                  	// #176
  402e64:	aa0103e2 	mov	x2, x1
  402e68:	aa0303e1 	mov	x1, x3
  402e6c:	97fff5f1 	bl	400630 <memcpy@plt>
  402e70:	910bc3a1 	add	x1, x29, #0x2f0
  402e74:	910343a0 	add	x0, x29, #0xd0
  402e78:	910083a2 	add	x2, x29, #0x20
  402e7c:	aa0203e8 	mov	x8, x2
  402e80:	97fff84d 	bl	400fb4 <createlist>
  402e84:	b94473a1 	ldr	w1, [x29, #1136]
  402e88:	b0000000 	adrp	x0, 403000 <main+0x790>
  402e8c:	911cc000 	add	x0, x0, #0x730
  402e90:	97fff608 	bl	4006b0 <printf@plt>
  402e94:	b94473b3 	ldr	w19, [x29, #1136]
  402e98:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402e9c:	910be001 	add	x1, x0, #0x2f8
  402ea0:	910083a0 	add	x0, x29, #0x20
  402ea4:	aa0103e3 	mov	x3, x1
  402ea8:	d2801601 	mov	x1, #0xb0                  	// #176
  402eac:	aa0103e2 	mov	x2, x1
  402eb0:	aa0303e1 	mov	x1, x3
  402eb4:	97fff5df 	bl	400630 <memcpy@plt>
  402eb8:	910083a0 	add	x0, x29, #0x20
  402ebc:	aa0003e1 	mov	x1, x0
  402ec0:	2a1303e0 	mov	w0, w19
  402ec4:	97fff9b3 	bl	401590 <bfs>
  402ec8:	140000bb 	b	4031b4 <main+0x944>
  402ecc:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402ed0:	91032000 	add	x0, x0, #0xc8
  402ed4:	b9408c00 	ldr	w0, [x0, #140]
  402ed8:	7100101f 	cmp	w0, #0x4
  402edc:	54000301 	b.ne	402f3c <main+0x6cc>  // b.any
  402ee0:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402ee4:	91032001 	add	x1, x0, #0xc8
  402ee8:	910903a0 	add	x0, x29, #0x240
  402eec:	aa0103e3 	mov	x3, x1
  402ef0:	d2804401 	mov	x1, #0x220                 	// #544
  402ef4:	aa0103e2 	mov	x2, x1
  402ef8:	aa0303e1 	mov	x1, x3
  402efc:	97fff5cd 	bl	400630 <memcpy@plt>
  402f00:	910903a0 	add	x0, x29, #0x240
  402f04:	910083a1 	add	x1, x29, #0x20
  402f08:	aa0103e8 	mov	x8, x1
  402f0c:	97fff77d 	bl	400d00 <create_4>
  402f10:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402f14:	91032001 	add	x1, x0, #0xc8
  402f18:	910083a0 	add	x0, x29, #0x20
  402f1c:	aa0103e3 	mov	x3, x1
  402f20:	d2804401 	mov	x1, #0x220                 	// #544
  402f24:	aa0103e2 	mov	x2, x1
  402f28:	aa0303e1 	mov	x1, x3
  402f2c:	97fff5c1 	bl	400630 <memcpy@plt>
  402f30:	910083a0 	add	x0, x29, #0x20
  402f34:	97fffabb 	bl	401a20 <prim>
  402f38:	1400009f 	b	4031b4 <main+0x944>
  402f3c:	b0000000 	adrp	x0, 403000 <main+0x790>
  402f40:	911d0000 	add	x0, x0, #0x740
  402f44:	97fff5cf 	bl	400680 <puts@plt>
  402f48:	17ffff43 	b	402c54 <main+0x3e4>
  402f4c:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402f50:	91032000 	add	x0, x0, #0xc8
  402f54:	b9408c00 	ldr	w0, [x0, #140]
  402f58:	7100041f 	cmp	w0, #0x1
  402f5c:	540000c0 	b.eq	402f74 <main+0x704>  // b.none
  402f60:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402f64:	91032000 	add	x0, x0, #0xc8
  402f68:	b9408c00 	ldr	w0, [x0, #140]
  402f6c:	71000c1f 	cmp	w0, #0x3
  402f70:	54000421 	b.ne	402ff4 <main+0x784>  // b.any
  402f74:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402f78:	91032001 	add	x1, x0, #0xc8
  402f7c:	910343a0 	add	x0, x29, #0xd0
  402f80:	aa0103e3 	mov	x3, x1
  402f84:	d2804401 	mov	x1, #0x220                 	// #544
  402f88:	aa0103e2 	mov	x2, x1
  402f8c:	aa0303e1 	mov	x1, x3
  402f90:	97fff5a8 	bl	400630 <memcpy@plt>
  402f94:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402f98:	910be001 	add	x1, x0, #0x2f8
  402f9c:	910bc3a0 	add	x0, x29, #0x2f0
  402fa0:	aa0103e3 	mov	x3, x1
  402fa4:	d2801601 	mov	x1, #0xb0                  	// #176
  402fa8:	aa0103e2 	mov	x2, x1
  402fac:	aa0303e1 	mov	x1, x3
  402fb0:	97fff5a0 	bl	400630 <memcpy@plt>
  402fb4:	910bc3a1 	add	x1, x29, #0x2f0
  402fb8:	910343a0 	add	x0, x29, #0xd0
  402fbc:	910083a2 	add	x2, x29, #0x20
  402fc0:	aa0203e8 	mov	x8, x2
  402fc4:	97fff7fc 	bl	400fb4 <createlist>
  402fc8:	d0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  402fcc:	910be001 	add	x1, x0, #0x2f8
  402fd0:	910083a0 	add	x0, x29, #0x20
  402fd4:	aa0103e3 	mov	x3, x1
  402fd8:	d2801601 	mov	x1, #0xb0                  	// #176
  402fdc:	aa0103e2 	mov	x2, x1
  402fe0:	aa0303e1 	mov	x1, x3
  402fe4:	97fff593 	bl	400630 <memcpy@plt>
  402fe8:	910083a0 	add	x0, x29, #0x20
  402fec:	97fffa1c 	bl	40185c <topsort>
  402ff0:	14000071 	b	4031b4 <main+0x944>
  402ff4:	b0000000 	adrp	x0, 403000 <main+0x790>
  402ff8:	911d4000 	add	x0, x0, #0x750
  402ffc:	97fff5a1 	bl	400680 <puts@plt>
  403000:	17ffff15 	b	402c54 <main+0x3e4>
  403004:	b0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  403008:	91032000 	add	x0, x0, #0xc8
  40300c:	b9408c00 	ldr	w0, [x0, #140]
  403010:	71000c1f 	cmp	w0, #0x3
  403014:	54000421 	b.ne	403098 <main+0x828>  // b.any
  403018:	b0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  40301c:	91032001 	add	x1, x0, #0xc8
  403020:	910343a0 	add	x0, x29, #0xd0
  403024:	aa0103e3 	mov	x3, x1
  403028:	d2804401 	mov	x1, #0x220                 	// #544
  40302c:	aa0103e2 	mov	x2, x1
  403030:	aa0303e1 	mov	x1, x3
  403034:	97fff57f 	bl	400630 <memcpy@plt>
  403038:	b0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  40303c:	910be001 	add	x1, x0, #0x2f8
  403040:	910bc3a0 	add	x0, x29, #0x2f0
  403044:	aa0103e3 	mov	x3, x1
  403048:	d2801601 	mov	x1, #0xb0                  	// #176
  40304c:	aa0103e2 	mov	x2, x1
  403050:	aa0303e1 	mov	x1, x3
  403054:	97fff577 	bl	400630 <memcpy@plt>
  403058:	910bc3a1 	add	x1, x29, #0x2f0
  40305c:	910343a0 	add	x0, x29, #0xd0
  403060:	910083a2 	add	x2, x29, #0x20
  403064:	aa0203e8 	mov	x8, x2
  403068:	97fff7d3 	bl	400fb4 <createlist>
  40306c:	b0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  403070:	910be001 	add	x1, x0, #0x2f8
  403074:	910083a0 	add	x0, x29, #0x20
  403078:	aa0103e3 	mov	x3, x1
  40307c:	d2801601 	mov	x1, #0xb0                  	// #176
  403080:	aa0103e2 	mov	x2, x1
  403084:	aa0303e1 	mov	x1, x3
  403088:	97fff56a 	bl	400630 <memcpy@plt>
  40308c:	910083a0 	add	x0, x29, #0x20
  403090:	97fffb8e 	bl	401ec8 <criticalpath>
  403094:	14000048 	b	4031b4 <main+0x944>
  403098:	90000000 	adrp	x0, 403000 <main+0x790>
  40309c:	911dc000 	add	x0, x0, #0x770
  4030a0:	97fff578 	bl	400680 <puts@plt>
  4030a4:	17fffeec 	b	402c54 <main+0x3e4>
  4030a8:	b0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  4030ac:	91032000 	add	x0, x0, #0xc8
  4030b0:	b9408c00 	ldr	w0, [x0, #140]
  4030b4:	71000c1f 	cmp	w0, #0x3
  4030b8:	54000301 	b.ne	403118 <main+0x8a8>  // b.any
  4030bc:	b0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  4030c0:	91032001 	add	x1, x0, #0xc8
  4030c4:	910903a0 	add	x0, x29, #0x240
  4030c8:	aa0103e3 	mov	x3, x1
  4030cc:	d2804401 	mov	x1, #0x220                 	// #544
  4030d0:	aa0103e2 	mov	x2, x1
  4030d4:	aa0303e1 	mov	x1, x3
  4030d8:	97fff556 	bl	400630 <memcpy@plt>
  4030dc:	910903a0 	add	x0, x29, #0x240
  4030e0:	910083a1 	add	x1, x29, #0x20
  4030e4:	aa0103e8 	mov	x8, x1
  4030e8:	97fff6b0 	bl	400ba8 <create_3>
  4030ec:	b0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  4030f0:	91032001 	add	x1, x0, #0xc8
  4030f4:	910083a0 	add	x0, x29, #0x20
  4030f8:	aa0103e3 	mov	x3, x1
  4030fc:	d2804401 	mov	x1, #0x220                 	// #544
  403100:	aa0103e2 	mov	x2, x1
  403104:	aa0303e1 	mov	x1, x3
  403108:	97fff54a 	bl	400630 <memcpy@plt>
  40310c:	910083a0 	add	x0, x29, #0x20
  403110:	97fffc0b 	bl	40213c <shortpath_dijkstra>
  403114:	14000028 	b	4031b4 <main+0x944>
  403118:	90000000 	adrp	x0, 403000 <main+0x790>
  40311c:	911e2000 	add	x0, x0, #0x788
  403120:	97fff558 	bl	400680 <puts@plt>
  403124:	17fffecc 	b	402c54 <main+0x3e4>
  403128:	b0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  40312c:	91032000 	add	x0, x0, #0xc8
  403130:	b9408c00 	ldr	w0, [x0, #140]
  403134:	71000c1f 	cmp	w0, #0x3
  403138:	54000301 	b.ne	403198 <main+0x928>  // b.any
  40313c:	b0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  403140:	91032001 	add	x1, x0, #0xc8
  403144:	910903a0 	add	x0, x29, #0x240
  403148:	aa0103e3 	mov	x3, x1
  40314c:	d2804401 	mov	x1, #0x220                 	// #544
  403150:	aa0103e2 	mov	x2, x1
  403154:	aa0303e1 	mov	x1, x3
  403158:	97fff536 	bl	400630 <memcpy@plt>
  40315c:	910903a0 	add	x0, x29, #0x240
  403160:	910083a1 	add	x1, x29, #0x20
  403164:	aa0103e8 	mov	x8, x1
  403168:	97fff690 	bl	400ba8 <create_3>
  40316c:	b0000080 	adrp	x0, 414000 <memcpy@GLIBC_2.17>
  403170:	91032001 	add	x1, x0, #0xc8
  403174:	910083a0 	add	x0, x29, #0x20
  403178:	aa0103e3 	mov	x3, x1
  40317c:	d2804401 	mov	x1, #0x220                 	// #544
  403180:	aa0103e2 	mov	x2, x1
  403184:	aa0303e1 	mov	x1, x3
  403188:	97fff52a 	bl	400630 <memcpy@plt>
  40318c:	910083a0 	add	x0, x29, #0x20
  403190:	97fffd03 	bl	40259c <shortpath_floyd>
  403194:	14000008 	b	4031b4 <main+0x944>
  403198:	90000000 	adrp	x0, 403000 <main+0x790>
  40319c:	911e2000 	add	x0, x0, #0x788
  4031a0:	97fff538 	bl	400680 <puts@plt>
  4031a4:	17fffeac 	b	402c54 <main+0x3e4>
  4031a8:	90000000 	adrp	x0, 403000 <main+0x790>
  4031ac:	911e8000 	add	x0, x0, #0x7a0
  4031b0:	97fff534 	bl	400680 <puts@plt>
  4031b4:	17fffe8d 	b	402be8 <main+0x378>

00000000004031b8 <__libc_csu_init>:
  4031b8:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  4031bc:	910003fd 	mov	x29, sp
  4031c0:	a901d7f4 	stp	x20, x21, [sp, #24]
  4031c4:	90000094 	adrp	x20, 413000 <__FRAME_END__+0xf84c>
  4031c8:	90000095 	adrp	x21, 413000 <__FRAME_END__+0xf84c>
  4031cc:	91374294 	add	x20, x20, #0xdd0
  4031d0:	913722b5 	add	x21, x21, #0xdc8
  4031d4:	a902dff6 	stp	x22, x23, [sp, #40]
  4031d8:	cb150294 	sub	x20, x20, x21
  4031dc:	f9001ff8 	str	x24, [sp, #56]
  4031e0:	2a0003f6 	mov	w22, w0
  4031e4:	aa0103f7 	mov	x23, x1
  4031e8:	9343fe94 	asr	x20, x20, #3
  4031ec:	aa0203f8 	mov	x24, x2
  4031f0:	97fff500 	bl	4005f0 <_init>
  4031f4:	b4000194 	cbz	x20, 403224 <__libc_csu_init+0x6c>
  4031f8:	f9000bb3 	str	x19, [x29, #16]
  4031fc:	d2800013 	mov	x19, #0x0                   	// #0
  403200:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  403204:	aa1803e2 	mov	x2, x24
  403208:	aa1703e1 	mov	x1, x23
  40320c:	2a1603e0 	mov	w0, w22
  403210:	91000673 	add	x19, x19, #0x1
  403214:	d63f0060 	blr	x3
  403218:	eb13029f 	cmp	x20, x19
  40321c:	54ffff21 	b.ne	403200 <__libc_csu_init+0x48>  // b.any
  403220:	f9400bb3 	ldr	x19, [x29, #16]
  403224:	a941d7f4 	ldp	x20, x21, [sp, #24]
  403228:	a942dff6 	ldp	x22, x23, [sp, #40]
  40322c:	f9401ff8 	ldr	x24, [sp, #56]
  403230:	a8c47bfd 	ldp	x29, x30, [sp], #64
  403234:	d65f03c0 	ret

0000000000403238 <__libc_csu_fini>:
  403238:	d65f03c0 	ret

Disassembly of section .fini:

000000000040323c <_fini>:
  40323c:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  403240:	910003fd 	mov	x29, sp
  403244:	a8c17bfd 	ldp	x29, x30, [sp], #16
  403248:	d65f03c0 	ret
